Low-Power Double Data Rate (LPDDR) emerged as a specialized high performance, low power memory for mobile phones. Since its first release in 2006, each new generation of LPDDR has delivered the bandwidth and capacity needed for major shifts in the mobile user experience. Once again, LPDDR is at the forefront of another key shift as the next wave of generative AI applications will be built into our mobile phones and laptops.

AI on endpoints is all about efficient inference. The process of employing trained AI models to make predictions or decisions requires specialized memory technologies with greater performance that are tailored to the unique demands of endpoint devices. Memory for AI inference on endpoints requires getting the right balance between bandwidth, capacity, power and compactness of form factor.

LPDDR evolved from DDR memory technology as a power-efficient alternative; LPDDR5, and the optional extension LPDDR5X, are the most recent updates to the standard. LPDDR5X is focused on improving performance, power, and flexibility; it offers data rates up to 8.533 Gbps, significantly boosting speed and performance. Compared to DDR5 memory, LPDDR5/5X limits the data bus width to 32 bits, while increasing the data rate. The switch to a quarter-speed clock, as compared to a half-speed clock in LPDDR4, along with a new feature – Dynamic Voltage Frequency Scaling – keeps the higher data rate LPDDR5 operation within the same thermal budget as LPDDR4-based devices.

Given the space considerations of mobiles, combined with greater memory needs for advanced applications, LPDDR5X can support capacities of up to 64GB by using multiple DRAM dies in a multi-die package. Consider the example of a 7B LLaMa 2 model: the model consumes 3.5GB of memory capacity if based on INT4. A LPDDR5X package of x64, with two LPDDR5X devices per package, provides an aggregate bandwidth of 68 GB/s and, therefore, a LLaMa 2 model can run inference at 19 tokens per second.

As demand for more memory performance grows, we see LPDDR5 evolve in the market with the major vendors announcing additional extensions to LPDDR5 known as LPDDR5T, with the T standing for turbo. LPDDR5T boosts performance to 9.6 Gbps enabling an aggregate bandwidth of 76.8 GB/s in a x64 package of multiple LPDDR5T stacks. Therefore, the above example of a 7B LLaMa 2 model can run inference at 21 tokens per second.

With its low power consumption and high bandwidth capabilities, LPDDR5 is a great choice of memory not just for cutting-edge mobile devices, but also for AI inference on endpoints where power efficiency and compact form factor are crucial considerations. Rambus offers a new LPDDR5T/5X/5 Controller IP that is fully optimized for use in applications requiring high memory throughput and low latency. The Rambus LPDDR5T/5X/5 Controller enables cutting-edge LPDDR5T memory devices and supports all third-party LPDDR5 PHYs. It maximizes bus bandwidth and minimizes latency via look-ahead command processing, bank management and auto-precharge. The controller can be delivered with additional cores such as the In-line ECC or Memory Analyzer cores to improve in-field reliability, availability and serviceability (RAS).

The post LPDDR Memory Is Key For On-Device AI Performance appeared first on Semiconductor Engineering.

The Ansys team is gearing up for an exciting time at DAC this week, where we’ll be sharing a whole new way of visualizing physical phenomena in 3D-IC designs, powered by NVIDIA Omniverse, a platform for developing OpenUSD and RTX-enabled 3D applications and workflows. Please attend our Exhibitor Forum session so we can show you the valuable design insights you can gain by interactively viewing surface currents, temperatures and mechanical deformations in a representative 3D-IC design.

Visualizing physical phenomena in 3D is a new paradigm for IC packaging signal and power integrity (SI/PI) engineers who are more familiar with schematics and 2D results plots (TDR, eye diagrams, SYZ parameters, etc). There’s a good reason for that – it really hasn’t been practical to save 3D physics data – or even to run full 3D simulations – for complex IC package designs until more recent (~5-10 years) advancements in Ansys solver technologies along with increasing accessibility to high performance compute power. I have had the pleasure of supporting a few early adopters in the SI/PI engineering community as they used 3D field plotting in HFSS to gain design insights that helped them avoid costly tape-out delays and chip re-spin. Their experiences motivate my desire to share this invaluable capability with the greater IC packaging design community.

I started my career using HFSS to design antennas for biomedical applications. Like me, the greater antenna and RF component design community has been plotting fields in 3D from Day 1 – I don’t know of any antenna engineer that hasn’t plotted a 3D radiation pattern after running an HFSS simulation. What I do know is that I’ve met hundreds of SI/PI engineers who have never plotted surface currents in their package or PCB models after running an HFSS simulation. And that must change.

…but why exactly? What value does one gain by plotting fields in 3D? If you don’t know what kind of design insights you gain by plotting fields, please allow me to show you because seeing is revealing.

Let’s say I send a signal from point A and it reflects off 3 different plates before returning back to point A:

Fig. 1: The plot below shows the received power from a sensor placed at Point A (the same position as the emitter). Can you tell which bump in this two 2D plot is the original signal returned back home?

Fig. 2: No? Neither can I. Even if you somehow guessed correctly, could you explain what caused all those other bumps with certainty?

With HFSS field plotting, everything becomes crystal clear:

Video 1: 3-bounce animation.

The original signal returns after a travel distance of 6 meters around the circle while the rest of the bumps result from other reflections – this is the kind of physical insight that a 2D plot simply can’t deliver.

Advanced packaging for 3D-IC design can’t be done with generic rules of thumb. To meet stringent specifications (operate at higher frequencies, speeds, and lower latency, power consumption), engineers are demanding the use of HFSS because its gold-standard reputation has come from countless validation studies comparing simulated results against measurement, and there is no room to compromise on accuracy for these very complex and costly designs. As more electronics are packed into tighter spaces, the risk for unwanted coupling between the different components (often stacked vertically) increases and being able to identify the true aggressors becomes more challenging. That’s when field visualization as a means to debug – i.e., uncover, learn, truly understand – what’s happening becomes an invaluable tool.

What exactly is causing unwanted radiation or reflections? What exactly is the source of noise coupling into this line? Are we seeing any current crowding on conductors or significant volume losses in dielectrics that may lead to thermal problems? Plot the fields and you will have the information required to diagnose issues and design the exact right solution – nothing more (over-designed), nothing less (failing design).

If you’re one of the early adopters who has plotted fields in highly complex designs, you will know that fields post-processing can be very graphics intensive – especially if you want to immerse yourself in the physical phenomena taking place in your design by plotting in a full 3D volume and cutting through the 3D space layer by layer. Ansys uses the enhanced graphics and visual rendering capabilities offered by NVIDIA Omniverse core technologies, available as APIs, to provide a seamlessly interactive and more intuitive experience, increasing accessibility to design insights that engineers can only gain by physics visualization.

I’m not asking my SI/PI engineering colleagues to ditch the schematics and 2D results plots – I just believe that they should (and inevitably will!) add 3D field plotting into their design process. The rise in design complexity coupled with advancements in Ansys and NVIDIA technologies is poised to make 3D field plotting – an invaluable yet heretofore underutilized tool in the world of signal and power integrity design – a practical requirement. For a first look into what will one day be commonplace design practice, please attend our Exhibitor Forum session on Wed., June 26, 1:45 PM -3:00 PM at DAC to experience our interactive demonstration of Ansys physics visualization in a representative 3D-IC design, powered by NVIDIA Omniverse.

The post Powering Next-Generation Insightful Design appeared first on Semiconductor Engineering.

The U.S. proposed new regulations to curtail American investments in Chinese technologies that pose a national security threat, specifically calling out semiconductors and microelectronics, quantum information technologies, and AI.

The draft regulations come nearly a year after the Biden administration issued an executive order prohibiting investments in sensitive technologies used to accelerate China’s military technologies.  “This proposed rule advances our national security by preventing the many benefits certain U.S. investments provide — beyond just capital — from supporting the development of sensitive technologies in countries that may use them to threaten our national security,” said Paul Rosen, assistant secretary of the treasury for investment security, in a release.

Prohibited Semiconductor Transactions

The 165-page proposal defines prohibited semiconductor transactions (pages 133-134), which include:

• EDA software for the design of ICs or advanced packaging;
• Front-end semiconductor fab equipment designed for performing the volume fabrication of ICs, including equipment used in the production stages from a blank wafer or substrate to a completed wafer or substrate;
• Equipment for performing volume advanced packaging;
• Commodity, material, software, or technology designed exclusively for use in or with EUV lithography equipment;
• Design of ICs for operation at or below 4.5 Kelvin, and ICs that meet or exceed performance criteria in Export Control Classification Number 3A090;
• Fabrication of logic ICs using a non-planar transistor architecture, or with a production technology node of 16/14 nanometers or less, including FD-SOI ICs;
• Fabrication of NAND with 128 layers or more, or DRAM ICs at 18nm half-pitch or less;
• Fabrication of gallium-based compound semiconductors, or ICs using graphene transistors or carbon nanotubes, and
• Any IC using advanced packaging techniques.

 

Prohibited AI And Supercomputing Transactions

Prohibited transactions for supercomputers and artificial intelligence (pages 134-135) include:

• Any supercomputer enabled by advanced ICs that can provide a theoretical compute capacity of 100 or more double-precision (64-bit) petaflops, or 200 or more single-precision (32-bit) petaflops of processing power within a 41,600 cubic foot or smaller envelope;
• Any quantum computer, or production of any of the critical components required to produce a quantum computer, such as a dilution refrigerator or two-stage pulse tube cryocooler;
• Quantum sensing platforms for military, government or mass-surveillance end use;
• Quantum network or quantum communication system, and
• AI for military end use, weapons targeting, target identification, and military decision-making.

Written comments are due by Aug. 4, 2024. The regulations are expected to be finalized this calendar year.

More Reading:
Chip Industry Week In Review
GF, BAE team up; $2B Czech SiC plant; SEMI’s capacity report; imec’s CFETs, beamforming transmitters; Germany chip plant postponed; EUV patterning advances; interconnect metals; plasma etch.

The post U.S. Proposes Restrictions On Tech Investments In China appeared first on Semiconductor Engineering.

Warpage is becoming a serious concern in advanced packaging, where a heterogeneous mix of materials can cause uneven stress points during assembly and packaging, and under real workloads in the field.

Warpage plays a critical role in determining whether an advanced package can be assembled successfully and meet long-term reliability targets. New advances, such as molding compounds with improved thermal properties, advanced modeling techniques, and creative architectures involving two molding steps are enabling greater control over package warpage, while also providing more flexibility to optimize a robust multi-chiplet system.

Warpage is the inevitable result of the mismatch in coefficients of thermal expansion (CTEs) between the silicon chip, molding compound, copper, polyimide, and other materials. It changes throughout the assembly process, and can cause cracking or delamination failures. The most vulnerable spots include low-k cores, which are subject to cracking and shorts, or non-wet failures in micro-bumps.

“One thing that’s very hot these days is the discussion around warpage and stress of the package,” said Kenneth Larsen, senior director of product management at Synopsys. “This is not only when you’re going through the manufacturing process, where you change temperatures. That can cause warpage. But it’s also when the device you’re building needs to be inserted into a socket. You can have issues around warpage there, as well.”

Even when warpage is effectively addressed during assembly and packaging, a device still may warp under heavy usage in the field. This is particularly true with heterogeneous designs, where chiplets are developed using different materials or processes, and where logic is concentrated in specific areas of an asymmetrical package.

The transition to multi-chiplet packaging is accelerating rapidly due to demands for ever-higher processing speeds and low latency, especially in mobile, automotive and high-performance compute/AI applications. Engineers increasingly are turning to modeling and simulation to understand temperature-dependent warpage, which can vary depending on die thickness, mold-to-silicon ratio, and substrate type. Organic substrates are very attractive because they are inexpensive and can be customized to any size, but they are much more flexible and susceptible to warpage than silicon substrates.

All these considerations point to the need for thermal and structural models of complex heterogeneous assemblies and packages. “Advanced modeling allows companies to simulate the behavior of different materials, thermal dynamics, and mechanical stresses during the assembly process,” said Mike Kelly, vice president of chiplets/FCBGA integration at Amkor. “Through this virtual experimentation, one can predict and mitigate potential challenges, ensuring that the final product meets stringent quality and reliability standards.”

How warpage happens
The assembly process includes multiple heating and cooling steps, which induce a certain amount of deformation between adjacent materials with different thermal and mechanical properties. In advanced packaging, warpage in the 100 micron range is not unheard of.

One of the reasons warpage is such a problem today is the large size of chiplets and the very tight process windows for chiplets, redistribution layers (RDLs), substrates, and bumps of various sizes. The relative expansion and contraction of neighboring materials depends on differences in the material’s CTE, which spells out the increase in size with each degree change of temperature (ppm/°C).

“Chiplets are typically relatively large die,” said Dick Otte, CEO of Promex Industries. “In the iPad, it’s 20 x 30 millimeters, with as many as 10,000 I/Os — usually copper pillar. Just simply taking a single die and putting it down on a substrate can be quite a challenge because the pitches are so small. So what’s critical for these assemblies is controlling warpage and planarity. It needs to stay planar through the whole reflow solder process to bridge that gap between the copper pillar and the contact on the circuit board without warping.”

Warpage can either happen upward, bending at the edges (smiling), or downward (crying), depending on the relative CTEs of the materials in the stack. Silicon, for example, is 2.8; copper is 17; FR4 PCB is 14 to 17 ppm/°C. The worst CTE mismatch is between a silicon interposer and an organic substrate.

It helps to envision stacks in packaging as groups of materials. “You have to look at the CTE of the materials and their reaction at temperatures, so you’ve got relatively low expansion copper on the top and solder at the bottom,” Otte said. “They’re kind of equal with a high expansion dielectric in the middle, so that when you heat this thing up, it kind of expands by the same amount. If you just put all the copper on the top, that thing is going to warp toward the copper side when you heat it up. Copper is 15 ppm per degree C. The organics are more like twice that, at 25 to 30 ppm/°C.

Other key metrics are the modulus, or the elasticity of a material, and the glass transition temperature (Tg), the temperature at which a material begins to flow. These values are related, too. For example, when it comes to the thermal behavior of polymers like epoxy molding compound (EMC), the modulus tends to plummet above its glass transition temperature. That happens because polymer chains tend to slide freely in the liquid state, whereas they are stiffer in a solid form.

In addition to solder reflow, warpage tends to occur at the post-molding curing step. Hung-Chun Yang and colleagues at ASE recently determined that die thickness substantially influences warpage levels measured at multiple steps in an existing process for chip-first fan-out chip on substrate package. [1] They noted that “severe wafer warpage occurred after curing, resulting in misalignment and difficulty in handling in the subsequent process.” To reduce package warpage, the team replaced a metal carrier/thin film approach with a glass carrier. The team also determined that a 3D finite element method (FEM) captures the warpage behavior and agreed well with actual test vehicle data.

Fig. 1: The glass carrier in the improved flow (right) induced less warpage than the original flow. Increasing the die thickness also dramatically reduced warpage. Source: ASE

The chip-first process begins with probing the fabricated wafers, thinning and then electroplating copper studs prior to sawing and placement of known good die in two schemes. The initial process used a metal carrier that is removed after molding and replaced with a thin film. The improved process uses a glass carrier that remained through molding, curing, mold grinding, RDL, and copper pillar processes, and then wass de-bonded.

Warpage reaches its maximum level during post-mold curing, and it changes most dramatically at the curing step and after glass carrier debonding. The glass carrier flow reduces warpage overall. In addition, the ASE engineers determined they can reduce warpage an additional 35% by increasing the wafer thickness from 0.54mm to 0.7mm.

A second strategy for reducing warpage involves using EMCs with different thermal properties, especially when the process calls for two molding steps. Amkor engineers recently evaluated the reliability performance of two high-performance multi-chiplet packages by modeling and fabricating two high-performance test vehicles. One used a module approximately the size of one reticle, containing 1 ASIC, 2 HBMs and 2 bridge die (33 x 26mm). The second module was 3 reticles in size, with 2 ASICs, 8 HBMs and 10 bridge dies (54 x 46mm). [2] Heejun Jang and colleagues at Amkor Technology Korea carried out modeling and simulation using the Ansys Parametric Design Language (APDL) version 16.1 simulator and compared results with test vehicles containing dummy dies.

Amkor’s die-last S-Connect process starts with a carrier wafer, on which copper studs for the bridge die and copper pillars are fabricated (see figure 2). The integrated passives and bridge die are embedded in the first mold, which is cured and then ground back. RDL is deposited on the mold and solder capture pads and dies attached to the pads using micro-bumps. Then, the solder is reflowed and underfilled. The second mold around the face-up die is cured and ground back, followed by C4 bumping on the bottom for flip-chip connect to the substrate. The simulation analyzes warpage with 9 combinations of 3 different EMCs with high, medium, and low CTEs (7 to 12 ppm below Tg, 22 to 46 ppm above Tg) and high-to-low glass transition temperatures (145°C to 175°C). [2]

Fig. 2: Process flow for S-Connect Package. Source: Amkor

Warpage as a function of EMC choice showed all materials followed the same smile pattern at room temperature, and cry pattern at high temperature (250°C). The EMCs with the lower CTEs caused less warpage. And in cases where the mold occupies more area relative to chip area, the warpage level is more pronounced. More importantly, the warpage levels were roughly 50% higher for 450µm die relative to 650µm-thick die. Interestingly, the thicker silicon die was 3X more effective in controlling warpage relative to EMC material selection on overall module warpage, so die thickness is the biggest lever in reducing warpage in cases where it can be increased.

Reliability testing is paramount once the package configuration is chosen. Amkor ran its advanced packaging test vehicles through moisture resistance testing, highly accelerated stress testing, thermal cycling condition B, and high temperature storage tests. These are needed to root out infant mortality issues, and cross-sectional analysis can reveal any cracks or latent defects that could precipitate into failures in field use.

While the above example may constitute a large multi-chiplet package today, package sizes are growing larger still, which means even more attention to warpage will be needed. More and more this will drive assembly lines toward digital twin or virtual representations to enable process and package optimization.

“By creating virtual representations of the semiconductor assembly line, one can identify potential areas of concern and optimize control strategies,” said Amkor’s Kelly. “Virtual fabrication in package assembly enables companies to assess the impact of design changes on manufacturing processes before physical prototypes are even created. This not only accelerates the product development cycle, but also minimizes the risk of costly errors.”

The early identification of potential bottlenecks further shortens cycle times, and enhances overall efficiency.

Conclusion
Going forward, even greater attention to mechanical and thermal properties will be required by teams comprised of designers and packaging engineers. “Tight tolerances in new packaging design require an accurate analysis of mechanical and electrical tolerances during stack up,” said Curtis Zwenger, vice president of engineering and technical marketing at Amkor. “Increasingly higher levels of process capability are required, with common metrics like CpK. Identification of these critical interactions in the design can be accomplished early in process development with this type of modeling. In turn, these analyses guide the investment of advanced process control to ensure process capability is maintained.”

References

1. C. Yang, et al, “Investigation of Wafer Warpage Evolution Based on Fan-out Chip-first Process,” 2024 International Conference on Electronics Packaging (ICEP), Toyama, Japan, 2024, pp. 151-152, doi: 10.23919/ICEP61562.2024.10535572.
2. H. Jang et al., “Reliability Performance of S-Connect Module (Bridge Technology) for Heterogeneous Integration Packaging,” 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 1027-1031, doi: 10.1109/ECTC51909.2023.00175.

Related Reading
What Works Best For Chiplets
Not all chiplets are interchangeable, and options will be limited.

The post Controlling Warpage In Advanced Packages appeared first on Semiconductor Engineering.

A new technical paper titled “NVM-Flip: Non-Volatile-Memory BitFlips on the System Level” was published by researchers at Ruhr-University Bochum, University of Duisburg-Essen, and Robert Bosch.

Abstract
“Emerging non-volatile memories (NVMs) are promising candidates to substitute conventional memories due to their low access latency, high integration density, and non-volatility. These superior properties stem from the memristor representing the centerpiece of each memory cell and is branded as the fourth fundamental circuit element. Memristors encode information in the form of its resistance by altering the physical characteristics of their filament. Hence, each memristor can store multiple bits increasing the memory density and positioning it as a potential candidate to replace DRAM and SRAM-based memories, such as caches.

However, new security risks arise with the benefits of these emerging technologies, like the recent NeuroHammer attack, which allows adversaries to deliberately flip bits in ReRAMs. While NeuroHammer has been shown to flip single bits within memristive crossbar arrays, the system-level impact remains unclear. Considering the significance of the Rowhammer attack on conventional DRAMs, NeuroHammer can potentially cause crucial damage to applications taking advantage of emerging memory technologies.

To answer this question, we introduce NVgem5, a versatile system-level simulator based on gem5. NVgem5 is capable of injecting bit-flips in eNVMs originating from NeuroHammer. Our experiments evaluate the impact of the NeuroHammer attack on main and cache memories. In particular, we demonstrate a single-bit fault attack on cache memories leaking the secret key used during the computation of RSA signatures. Our findings highlight the need for improved hardware security measures to mitigate the risk of hardware-level attacks in computing systems based on eNVMs.”

Find the technical paper here. Published June 2024.

Felix Staudigl, Jan Philipp Thoma, Christian Niesler, Karl Sturm, Rebecca Pelke, Dominik Germek, Jan Moritz Joseph, Tim Güneysu, Lucas Davi, and Rainer Leupers. 2024. NVM-Flip: Non-Volatile-Memory BitFlips on the System Level. In Proceedings of the 2024 ACM Workshop on Secure and Trustworthy Cyber-Physical Systems (SaT-CPS ’24). Association for Computing Machinery, New York, NY, USA, 11–20. https://doi.org/10.1145/3643650.3658606

The post NeuroHammer Attacks on ReRAM-Based Memories appeared first on Semiconductor Engineering.

A new technical paper titled “IR drop Prediction Based on Machine Learning and Pattern Reduction” was published by researchers at National Tsing Hua University, National Taiwan University of Science and Technology, and MediaTek.

Abstract (partial)
“In this paper, we propose a machine learning-based method to predict IR drop levels and present an algorithm for reducing simulation patterns, which could reduce the time and computing resources required for IR drop analysis within the ECO flow. Experimental results show that our approach can reduce the number of patterns by approximately 50%, thereby decreasing the analysis time while maintaining accuracy.”

Find the technical paper here. Published June 2024.

Yong-Fong Chang, Yung-Chih Chen, Yu-Chen Cheng, Shu-Hong Lin, Che-Hsu Lin, Chun-Yuan Chen, Yu-Hsuan Chen, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Shih-Chieh Chang, Yi-Ting Li, and Chun-Yao Wang. 2024. IR drop Prediction Based on Machine Learning and Pattern Reduction. In Proceedings of the Great Lakes Symposium on VLSI 2024 (GLSVLSI ’24). Association for Computing Machinery, New York, NY, USA, 516–519. https://doi.org/10.1145/3649476.3658775

The post ML Method To Predict IR Drop Levels appeared first on Semiconductor Engineering.

BAE Systems and GlobalFoundries are teaming up to strengthen the supply of chips for national security programs, aligning technology roadmaps and collaborating on innovation and manufacturing. Focus areas include advanced packaging, GaN-on-silicon chips, silicon photonics, and advanced technology process development.

Onsemi plans to build a $2 billion silicon carbide production plant in the Czech Republic. The site would produce smart power semiconductors for electric vehicles, renewable energy technology, and data centers.

The global chip manufacturing industry is projected to boost capacity by 6% in 2024 and 7% in 2025, reaching 33.7 million 8-inch (200mm) wafers per month, according to SEMI‘s latest World Fab Forecast report. Leading-edge capacity for 5nm nodes and below is expected to grow by 13% in 2024, driven by AI demand for data center applications. Additionally, Intel, Samsung, and TSMC will begin producing 2nm chips using gate-all-around (GAA) FETs next year, boosting leading-edge capacity by 17% in 2025.

At the IEEE Symposium on VLSI Technology & Circuits, imec introduced:

• Functional CMOS-based CFETs with stacked bottom and top source/drain contacts.
• CMOS-based 56Gb/s zero-IF D-band beamforming transmitters to support next-gen short-range, high-speed wireless services at frequencies above 100GHz.
• ADCs for base stations and handsets, a key step toward scalable, high-performance beyond-5G solutions, such as cloud-based AI and extended reality apps.

Quick links to more news:

Global
In-Depth
Market Reports
Education and Training
Security
Product News
Research
Events and Further Reading

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Global

Wolfspeed postponed plans to construct a $3 billion chip plant in Germany, underscoring the EU‘s challenges in boosting semiconductor production, reports Reuters. The North Carolina-based company cited reduced capital spending due to a weakened EV market, saying it now aims to start construction in mid-2025, two years later than 0riginally planned.

Micron is building a pilot production line for high-bandwidth memory (HBM) in the U.S., and considering HBM production in Malaysia to meet growing AI demand, according to a Nikkei report. The company is expanding HBM R&D facilities in Boise, Idaho, and eyeing production capacity in Malaysia, while also enhancing its largest HBM facility in Taichung, Taiwan.

Kioxia restored its Yokkaichi and Kitakami plants in Japan to full capacity, ending production cuts as the memory market recovers, according to Nikkei. The company, which is focusing on NAND flash production, has secured new bank credit support, including refinancing a ¥540 billion loan and establishing a ¥210 billion credit line. Kioxia had reduced output by more than 30% in October 2022 due to weak smartphone demand.

Europe’s NATO Innovation Fund announced its first direct investments, which includes semiconductor materials. Twenty-three NATO allies co-invested in this over $1B fund devoted to address critical defense and security challenges.

The second meeting of the U.S.–India Initiative on Critical and Emerging Technology (iCET) was held in New Delhi, with various funding and initiatives announced to support semiconductor technology, next-gen telecommunications, connected and autonomous vehicles, ML, and more.

Amazon announced investments of €10 billion in Germany to drive innovation and support the expansion of its logistics network and cloud infrastructure.

Quantum Machines opened the Israeli Quantum Computing Center (IQCC) research facility, backed by the Israel Innovation Authority and located at Tel Aviv University. Also, Israel-based Classiq is collaborating with NVIDIA and BMW, using quantum computing to find the optimal automotive architecture of electrical and mechanical systems.

Global data center vacancy rates are at historic lows, and power availability is becoming less available, according to a Siemens report featured on Broadband Breakfast. The company called for an influx of financing to find new ways to optimize data center technology and sustainability.

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In-Depth

Semiconductor Engineering published its Manufacturing, Packaging & Materials newsletter this week, featuring these top stories:

• Single Vs. Multi-Patterning Advancements For EUV
• Precise Control Of Copper Plating And CMP
• Ruthenium Interconnects On Tap
• Opportunities Grow For GPU Acceleration

More reporting this week:

• IC Industry’s Growing Role In Sustainability
• What’s Missing In Test

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Market Reports

Renesas completed its acquisition of Transphorm and will immediately start offering GaN-based power products and reference designs to meet the demand for wide-bandgap (WBG) chips.

Revenues for the top five wafer fab equipment (WFE) companies fell 9% YoY in Q1 2024, according to Counterpoint. This was offset partially by increased demand for NAND and DRAM, which increased 33% YoY, and strong growth in sales to China, which were up 116% YoY.

The SiC power devices industry saw robust growth in 2023, primarily driven by the BEV market, according to TrendForce. The top five suppliers, led by ST with a 32.6% market share and onsemi in second place, accounted for 91.9% of total revenue. However, the anticipated slowdown in BEV sales and weakening industrial demand are expected to significantly decelerate revenue growth in 2024. 

About 30% of vehicles produced globally will have E/E architectures with zonal controllers by 2032, according to McKinsey & Co. The market for automotive micro-components and logic semiconductors is predicted to reach $60 billion in 2032, and the overall automotive semiconductor market is expected to grow from $60 billion to $140 billion in the same period, at a 10% CAGR.

The automotive processor market generated US$20 billion in revenue in 2023, according to Yole. US$7.8 billion was from APUs and FPGAs and $12.2 billion was from MCUs. The ADAS and infotainment processors market was worth US$7.8 billion in 2023 and is predicted to grow to $16.4 billion by 2029 at a 13% CAGR. The market for ADAS sensing is expected to grow at a 7% CAGR.

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Security

The CHERI Alliance was established to drive adoption of memory safety and scalable software compartmentalization via the security technology CHERI, or Capability Hardware Enhanced RISC Instructions. Founding members include Capabilities Limited, Codasip, the FreeBSD Foundation, lowRISC, SCI Semiconductor, and the University of Cambridge.

In security research:

• Japan and China researchers explored a NAND-XOR ring oscillator structure to design an entropy source architecture for a true random number generator (TRNG).
• University of Toronto and Carleton University researchers presented a survey examining how hardware is applied to achieve security and how reported attacks have exploited certain defects in hardware.
• University of North Texas and Texas Woman’s University researchers explored the potential of hardware security primitive Physical Unclonable Functions (PUF) for mitigation of visual deepfakes.
• Villanova University researchers proposed the Boolean DERIVativE attack, which generalizes Boolean domain leakage.

Post-quantum cryptography firm PQShield raised $37 million in Series B funding.

Former OpenAI executive, Ilya Sutskever, who quit over safety concerns, launched Safe Superintelligence Inc. (SSI).

EU industry groups warned the European Commission that its proposed cybersecurity certification scheme (EUCS) for cloud services should not discriminate against Amazon, Google, and Microsoft, reported Reuters.

Cyber Europe tested EU cyber preparedness in the energy sector by simulating a series of large-scale cyber incidents in an exercise organized by the European Union Agency for Cybersecurity (ENISA).

The Cybersecurity and Infrastructure Security Agency (CISA) issued a number of alerts/advisories.

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Education and Training

New York non-profit NY CREATES and South Korea’s National Nano Fab Center partnered to develop a hub for joint research, aligned technology services, testbed support, and an engineer exchange program to bolster chips-centered R&D, workforce development, and each nation’s high-tech ecosystem.

New York and the Netherlands agreed on a partnership to promote sustainability within the semiconductor industry, enhance workforce development, and boost semiconductor R&D.

Rapidus is set to send 200 engineers to AI chip developer Tenstorrent in the U.S. for training over the next five years, reports Nikkei. This initiative, led by Japan’s Leading-edge Semiconductor Technology Center (LSTC), aims to bolster Japan’s AI chip industry.

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Product News

UMC announced its 22nm embedded high voltage (eHV) technology platform for premium smartphone and mobile device displays. The 22eHV platform reduces core device power consumption by up to 30% compared to previous 28nm processes. Die area is reduced by 10% with the industry’s smallest SRAM bit cells.​

Alphawave Semi announced a new 9.2 Gbps HBM3E sub-system silicon platform capable of 1.2 terabytes per second. Based on the HBM3E IP, the sub-system is aimed at addressing the demand for ultra-high-speed connectivity in high-performance compute applications.

Movellus introduced the Aeonic Power product family for on-die voltage regulation, targeting the challenging area of power delivery.

Cadence partnered with Semiwise and sureCore to develop new cryogenic CMOS circuits with possible quantum computing applications. The circuits are based on modified transistors found in the Cadence Spectre Simulation Platform and are capable of processing analog, mixed-signal, and digital circuit simulation and verification at cryogenic temperatures.

Renesas launched R-Car Open Access (RoX), an integrated development platform for software-defined vehicles (SDVs), designed for Renesas R-Car SoCs and MCUs with tools for deployment of AI applications, reducing complexity and saving time and money for car OEMs and Tier 1s.

Infineon released industry-first radiation-hardened 1 and 2 Mb parallel interface ferroelectric-RAM (F-RAM) nonvolatile memory devices, with up to 120 years of data retention at 85-degree Celsius, along with random access and full memory write at bus speeds. Plus, a CoolGaN Transistor 700 V G4 product family for efficient power conversion up to 700 V, ideal for consumer chargers and notebook adapters, data center power supplies, renewable energy inverters, and more.

Ansys adopted NVIDIA’s Omniverse application programming interfaces for its multi-die chip designers. Those APIs will be used for 5G/6G, IoT, AI/ML, cloud computing, and autonomous vehicle applications. The company also announced ConceptEV, an SaaS solution for automotive concept design for EVs.

Fig. 1: Field visualization of 3D-IC with Omniverse. Source: Ansys

QP Technologies announced a new dicing saw for its manufacturing line that can process a full cassette of 300mm wafers 7% faster than existing tools, improving throughput and productivity.

NXP introduced its SAF9xxx of audio DSPs to support the demand for AI-based audio in software-defined vehicles (SDVs) by using Cadence’s Tensilica HiFi 5 DSPs combined with dedicated neural-network engines and hardware-based accelerators.

Avionyx, a provider of software lifecycle engineering in the aerospace and safety-critical systems sector, partnered with Siemens and will leverage its Polarion application lifecycle management (ALM) tool. Also, Dovetail Electric Aviation adopted Siemens Xcelerator to support sustainable aviation.

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Research

Researchers from imec and KU Leuven released a +70 page paper “Selecting Alternative Metals for Advanced Interconnects,” addressing interconnect resistance and reliability.

A comprehensive review article — “Future of plasma etching for microelectronics: Challenges and opportunities” — was created by a team of experts from the University of Maryland, Lam Research, IBM, Intel, and many others.

Researchers from the Institut Polytechnique de Paris’s Laboratory of Condensed Matter for Physics developed an approach to investigate defects in semiconductors. The team “determined the spin-dependent electronic structure linked to defects in the arrangement of semiconductor atoms,” the first time this structure has been measured, according to a release.

Lawrence Berkeley National Laboratory-led researchers developed a small enclosed chamber that can hold all the components of an electrochemical reaction, which can be paired with transmission electron microscopy (TEM) to generate precise views of a reaction at atomic scale, and can be frozen to stop the reaction at specific time points. They used the technique to study a copper catalyst.

The Federal Drug Administration (FDA) approved a clinical trial to test a device with 1,024 nanoscale sensors that records brain activity during surgery, developed by engineers at the University of California San Diego (UC San Diego).

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Events and Further Reading

Find upcoming chip industry events here, including:

Event	Date	Location
Standards for Chiplet Design with 3DIC Packaging (Part 2)	Jun 21	Online
DAC 2024	Jun 23 – 27	San Francisco
RISC-V Summit Europe 2024	Jun 24 – 28	Munich
Leti Innovation Days 2024	Jun 25 – 27	Grenoble, France
ISCA 2024	Jun 29 – Jul 3	Buenos Aires, Argentina
SEMICON West	Jul 9 – 11	San Francisco
Flash Memory Summit	Aug 6 – 8	Santa Clara, CA
USENIX Security Symposium	Aug 14 – 16	Philadelphia, PA
Hot Chips 2024	Aug 25- 27	Stanford University
Find All Upcoming Events Here

Upcoming webinars are here.

Semiconductor Engineering’s latest newsletters:

Automotive, Security and Pervasive Computing
Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials

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The post Chip Industry Week In Review appeared first on Semiconductor Engineering.

A technical paper titled “Substrate Embedded Power Electronics Packaging for Silicon Carbide MOSFETs” was published by researchers at University of Cambridge, University of Warwick, Chongqing University, and SpaceX.

Abstract:

“This paper proposes a new power electronic packaging for discrete dies, namely Standard Cell which consists of a step-etched active metal brazed (AMB) substrate and a flexible printed circuit board (flex-PCB). The standard cell exhibits high thermal conductivity, complete electrical insulation, and low stray inductance, thereby enhancing the performance of SiC MOSFET devices. The standard cell has a stray power loop inductance of less than 1 nH and a gate loop inductance of less than 1.5 nH . The standard cell has a flat body with surface-mounting electrical connections on one side and direct thermal connections on the other. The use of flex-PCB die interconnection enables maximum utilization of source pads while providing a flexible gate-source connection and the converter PCB. This paper presents the design concept of the standard cell and experimentally validates its effectiveness in a converter system.”

Find the technical paper here. Published May 2024.

A. Janabi et al., “Substrate Embedded Power Electronics Packaging for Silicon Carbide MOSFETs,” in IEEE Transactions on Power Electronics, doi: 10.1109/TPEL.2024.3396779.

Related Reading
Big Shifts In Power Electronics Packaging
Packages are becoming more complex to endure high power, high temperature conditions across a variety of applications.
Power Semiconductors: A Deep Dive Into Materials, Manufacturing & Business
Premium Content: How these devices are made and work, challenges in manufacturing, related startups, as well as the reasons why so much effort and resources are being spent to develop new materials, and new processes.</

The post Power Electronic Packaging for Discrete Dies appeared first on Semiconductor Engineering.

A technical paper titled “Programmable Nonlinear Quantum Photonic Circuits” was published by researchers at Niels Bohr Institute, University of Copenhagen, University of Bristol, and Ruhr-Universitat Bochum.

Abstract:

“The lack of interactions between single photons prohibits direct nonlinear operations in quantum optical circuits, representing a central obstacle in photonic quantum technologies. Here, we demonstrate multi-mode nonlinear photonic circuits where both linear and direct nonlinear operations can be programmed with high precision at the single-photon level. Deterministic nonlinear interaction is realized with a tunable quantum dot embedded in a nanophotonic waveguide mediating interactions between individual photons within a temporal linear optical interferometer. We demonstrate the capability to reprogram the nonlinear photonic circuits and implement protocols where strong nonlinearities are required, in particular for quantum simulation of anharmonic molecular dynamics, thereby showcasing the new key functionalities enabled by our technology.”

Find the technical paper here. Published May 2024 (preprint).

Nielsen, Kasper H., Ying Wang, Edward Deacon, Patrik I. Sund, Zhe Liu, Sven Scholz, Andreas D. Wieck et al. “Programmable Nonlinear Quantum Photonic Circuits.” arXiv preprint arXiv:2405.17941 (2024).

Related Reading
The Race Toward Quantum Advantage
Enormous amounts of money have been invested into quantum computing, but so far it has not surpassed conventional computers. When will that change?
Photonics: The Former And Future Solution
Twenty-five years ago, photonics was supposed to be the future of high technology. Has that future finally arrived?

The post Demonstrating Programmable Nonlinear Quantum Photonic ICs appeared first on Semiconductor Engineering.

A technical paper titled “On Hardware-efficient Inference in Probabilistic Circuits” was published by researchers at Aalto University and UCLouvain.

Abstract:

“Probabilistic circuits (PCs) offer a promising avenue to perform embedded reasoning under uncertainty. They support efficient and exact computation of various probabilistic inference tasks by design. Hence, hardware-efficient computation of PCs is highly interesting for edge computing applications. As computations in PCs are based on arithmetic with probability values, they are typically performed in the log domain to avoid underflow. Unfortunately, performing the log operation on hardware is costly. Hence, prior work has focused on computations in the linear domain, resulting in high resolution and energy requirements. This work proposes the first dedicated approximate computing framework for PCs that allows for low-resolution logarithm computations. We leverage Addition As Int, resulting in linear PC computation with simple hardware elements. Further, we provide a theoretical approximation error analysis and present an error compensation mechanism. Empirically, our method obtains up to 357x and 649x energy reduction on custom hardware for evidence and MAP queries respectively with little or no computational error.”

Find the technical paper here. Published May 2024 (preprint). CODE: https://github.com/lingyunyao/AAI_Probabilistic_Circuits

Yao, Lingyun, Martin Trapp, Jelin Leslin, Gaurav Singh, Peng Zhang, Karthekeyan Periasamy, and Martin Andraud. “On Hardware-efficient Inference in Probabilistic Circuits.” arXiv preprint arXiv:2405.13639 (2024).

Related Reading
Architecting Chips For High-Performance Computing
Data center IC designs are evolving, based on workloads, but making the tradeoffs for those workloads is not always straightforward.
AI Tradeoffs At The Edge
The best ways to optimize AI efficiency today, and other options under development.

The post Dedicated Approximate Computing Framework To Efficiently Compute PCs On Hardware appeared first on Semiconductor Engineering.