FreshRSS
❌

Zobrazení pro čtení

Jsou dostupné nové články, klikněte pro obnovení stránky.

Chip Industry Technical Paper Roundup: August 20

✇Semiconductor Engineering
Od: Linda Christensen

New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node Samsung Electronics and Kyungpook National University (KNU)
Search-in-Memory (SiM): Reliable, Versatile, and Efficient Data Matching in SSD’s NAND Flash Memory Chip for Data Indexing Acceleration TU Dortmund, Academia Sinica, and National Taiwan University
Achieving Sustainability in the Semiconductor Industry: The Impact of Simulation and AI Lam Research
HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory Chalmers University of Technology and ZeroPoint Technologies
Retention-aware zero-shifting technique for Tiki-Taka algorithm-based analog deep learning accelerator Pohang University of Science and Technology, Korea University, and Kyungpook National University
Improvement of Contact Resistance and 3D Integration of 2D Material Field-Effect Transistors Using Semi-Metallic PtSe2 Contacts Yonsei University, Korea Advanced Institute of Science and Technology (KAIST), Lincoln University College, Korea Institute of Science and Technology (KIST), and Ewha Womans University
Ultra-steep slope cryogenic FETs based on bilayer graphene RWTH Aachen University, Forschungszentrum Julich, National Institute for Materials Science (Japan), and AMO GmbH

More Reading
Technical Paper Library home

The post Chip Industry Technical Paper Roundup: August 20 appeared first on Semiconductor Engineering.

U.S. Proposes Restrictions On Tech Investments In China

✇Semiconductor Engineering
Od: Linda Christensen

The U.S. proposed new regulations to curtail American investments in Chinese technologies that pose a national security threat, specifically calling out semiconductors and microelectronics, quantum information technologies, and AI.

The draft regulations come nearly a year after the Biden administration issued an executive order prohibiting investments in sensitive technologies used to accelerate China’s military technologies.  “This proposed rule advances our national security by preventing the many benefits certain U.S. investments provide — beyond just capital — from supporting the development of sensitive technologies in countries that may use them to threaten our national security,” said Paul Rosen, assistant secretary of the treasury for investment security, in a release.

Prohibited Semiconductor Transactions

The 165-page proposal defines prohibited semiconductor transactions (pages 133-134), which include:

  • EDA software for the design of ICs or advanced packaging;
  • Front-end semiconductor fab equipment designed for performing the volume fabrication of ICs, including equipment used in the production stages from a blank wafer or substrate to a completed wafer or substrate;
  • Equipment for performing volume advanced packaging;
  • Commodity, material, software, or technology designed exclusively for use in or with EUV lithography equipment;
  • Design of ICs for operation at or below 4.5 Kelvin, and ICs that meet or exceed performance criteria in Export Control Classification Number 3A090;
  • Fabrication of logic ICs using a non-planar transistor architecture, or with a production technology node of 16/14 nanometers or less, including FD-SOI ICs;
  • Fabrication of NAND with 128 layers or more, or DRAM ICs at 18nm half-pitch or less;
  • Fabrication of gallium-based compound semiconductors, or ICs using graphene transistors or carbon nanotubes, and
  • Any IC using advanced packaging techniques.

 

Prohibited AI And Supercomputing Transactions

Prohibited transactions for supercomputers and artificial intelligence (pages 134-135) include:

  • Any supercomputer enabled by advanced ICs that can provide a theoretical compute capacity of 100 or more double-precision (64-bit) petaflops, or 200 or more single-precision (32-bit) petaflops of processing power within a 41,600 cubic foot or smaller envelope;
  • Any quantum computer, or production of any of the critical components required to produce a quantum computer, such as a dilution refrigerator or two-stage pulse tube cryocooler;
  • Quantum sensing platforms for military, government or mass-surveillance end use;
  • Quantum network or quantum communication system, and
  • AI for military end use, weapons targeting, target identification, and military decision-making.

Written comments are due by Aug. 4, 2024. The regulations are expected to be finalized this calendar year.

More Reading:
Chip Industry Week In Review
GF, BAE team up; $2B Czech SiC plant; SEMI’s capacity report; imec’s CFETs, beamforming transmitters; Germany chip plant postponed; EUV patterning advances; interconnect metals; plasma etch.

The post U.S. Proposes Restrictions On Tech Investments In China appeared first on Semiconductor Engineering.

Chip Industry Technical Paper Roundup: June 10

✇Semiconductor Engineering
Od: Linda Christensen

New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors Carnegie Mellon University
Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core University of Southampton
High temperature stability of regrown and alloyed Ohmic contacts to AlGaN/GaN heterostructure up to 500 °C MIT, Technology Innovation Institute, Ohio State University, Rice University and Bangladesh University of Engineering and Technology
Comparative Analysis of Thermal Properties in Molybdenum Substrate to Silicon and Glass for a System-on-Foil Integration Rochester Institute of Technology and Lux Semiconductors
Modelling thermomechanical degradation of moulded electronic packages using physics-based digital twin Delft University of Technology and NXP Semiconductors
On the quality of commercial chemical vapour deposited hexagonal boron nitride KAUST and the National Institute for Materials Science in Japan
CMOS IC Solutions for the 77 GHz Radar Sensor in Automotive Applications STMicroelectronics and University of Catania
Imperceptible augmentation of living systems with organic bioelectronic fibres University of Cambridge and University of Macau

More Reading
Technical Paper Library home

The post Chip Industry Technical Paper Roundup: June 10 appeared first on Semiconductor Engineering.

Chip Industry Technical Paper Roundup: May 13

✇Semiconductor Engineering
Od: Linda Christensen

New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
Cross-layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search Georgia Tech
An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs University of California Santa Barbara
Efficient Approaches for GEMM Acceleration on Leading AI-Optimized FPGAs University of Texas at Austin and Arizona State University
Explaining EDA synthesis errors with LLMs University of New South Wales and University of Calgary
Materials for High Temperature Digital Electronics University of Pennsylvania, Air Force Research Laboratory, and Ozark Integrated Circuits
Synthesis of goldene comprising single-atom layer gold Linköping University
Thermal Crosstalk Modelling and Compensation Methods for Programmable Photonic Integrated Circuits Technical University of Denmark and iPronics Programmable Photonics

More Reading
Technical Paper Library home

The post Chip Industry Technical Paper Roundup: May 13 appeared first on Semiconductor Engineering.

❌