Samsung was in a spot of worry a few months ago, as its high-bandwidth memory (HBM) chips hadn't received Nvidia's certification for months. A few weeks ago, Samsung's HBM3 chips reportedly received Nvidia's certification for the Chinese market. However, even before the certification, Chinese firms had been reportedly stockpiling Samsung's HBM chips for months.

Chinese firms Baidu and Huawei have been reportedly stockpiling Samsung HBM chips for AI accelerators

According to a report from Reuters, Chinese tech giants Baidu and Huawei have been buying HBM chips from Samsung since earlier this year. The companies ramped up their purchases in anticipation of possible US curbs on exporting critical semiconductor chips to Chinese firms. The report claims that Chinese firms account for nearly 30% of Samsung's HBM chip sales globally.

It is reported that US authorities are planning to impose additional restrictions on chip shipments to China. The US already has curbs that restrict semiconductor chip firms from exporting 5nm (or more advanced) chips to be sold to Chinese firms. Newer export rules from the US may have specific parameters to restrict the export of HBM chips, which are crucial in AI processing.

Almost all AI accelerators, including AMD and Nvidia ones, are paired with HBM memory chips for faster data transfer. The only firms in the world that make HBM chips are Micron, Samsung, and SK Hynix. While HBM3E is the most advanced HBM chip right now, Chinese firms have been primarily buying HBM2E chips, which are two generations older.

Since Micron's and SK Hynix's HBM manufacturing capacities have been fully booked by US-based tech firms, Chinese firms are dependent on Samsung's HBM chips. Haawking and Tencent are also said to be among those who bought Samsung's HBM chips. If the US brings additional restrictions on the supply of HBM chips to the Chinese market, Samsung might face business issues.

Apparently, Chinese firm CXMT has been developing HBM2-grade memory chips that are three generations behind. By the time they start using homemade HBM2 chips, Micron, Samsung, and SK Hynix would have released HBM4 chips.

Image Credits: Samsung

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Samsung has unveiled the world's thinnest LPDDR5X DRAM chip, which is just 0.65mm thin, or as thin as a fingernail. This chip is made for high-end smartphones, which typically have an onboard neural processing unit (NPU) for on-device AI processing.

Samsung's newest LPDDR5X DRAM is just 0.65mm thin, making it the world's thinnest in its segment

The newest LPDDR5X DRAM chip from Samsung is the world's thinnest 12nm-class chip. It is available in 12GB and 16GB capacities. This chip is made using four stacked layers, each containing two LPDDR DRAM chips. Due to its thin profile, it offers more space in mobile devices, allowing for a better thermal design. According to Samsung, its new memory chip improves heat resistance by up to 21.2% compared to the previous-generation LPDDR5X chip.

Samsung optimized the printed circuit board (PCB), epoxy molding compound (EMC), and the back-lapping process to minimize the chip's height. The company plans to start supplying its new chip to smartphone manufacturers soon. It also announced that it will soon start making 24GB (6-layer) and 32GB (8-layer) LPDDR DRAM chips for future mobile devices.

YongCheol Bae, the Executive VP of Samsung's Memory Product Planning team, said, “Samsung’s LPDDR5X DRAM sets a new standard for high-performance on-device AI solutions, offering not only superior LPDDR performance but also advanced thermal management in an ultra-compact package. We are committed to continuous innovation through close collaboration with our customers, delivering solutions that meet the future needs of the low-power DRAM market.”

Image Credits: Samsung

The post Samsung’s new smartphone memory chip is as thin as a fingernail appeared first on SamMobile.

New developments and innovations in metrology and inspection will enable chipmakers to identify and address defects faster and with greater accuracy than ever before, all of which will be required at future process nodes and in densely-packed assemblies of chiplets.

These advances will affect both front-end and back-end processes, providing increased precision and efficiency, combined with artificial intelligence/machine learning and big data analytics. These kinds of improvements will be crucial for meeting the industry’s changing needs, enabling deeper insights and more accurate measurements at rates suitable for high-volume manufacturing. But gaps still need to be filled, and new ones are likely to show up as new nodes and processes are rolled out.

“As semiconductor devices become more complex, the demand for high-resolution, high-accuracy metrology tools increases,” says Brad Perkins, product line manager at Nordson Test & Inspection. “We need new tools and techniques that can keep up with shrinking geometries and more intricate designs.”

The shift to high-NA EUV lithography (0.55 NA EUV) at the 2nm node and beyond is expected to exacerbate stochastic variability, demanding more robust metrology solutions on the front end. Traditional critical dimension (CD) measurements alone are insufficient for the level of analysis required. Comprehensive metrics, including line-edge roughness (LER), line-width roughness (LWR), local edge-placement error (LEPE), and local CD uniformity (LCDU), alongside CD measurements, are necessary for ensuring the integrity and performance of advanced semiconductor devices. These metrics require sophisticated tools that can capture and analyze tiny variations at the nanometer scale, where even slight discrepancies can significantly impact device functionality and yield.

“Metrology is now at the forefront of yield, especially considering the current demands for DRAM and HBM,” says Hamed Sadeghian, president and CEO of Nearfield Instruments. “The next generations of HBMs are approaching a stage where hybrid bonding will be essential due to the increasing stack thickness. Hybrid bonding requires high resolutions in vertical directions to ensure all pads, and the surface height versus the dielectric, remain within nanometer-scale process windows. Consequently, the tools used must be one order of magnitude more precise.”

To address these challenges, companies are developing hybrid metrology systems that combine various measurement techniques for a comprehensive data set. Integrating scatterometry, electron microscopy, and/or atomic force microscopy allows for more thorough analysis of critical features. Moreover, AI and ML algorithms enhance the predictive capabilities of these tools, enabling process adjustments.

“Our customers who are pushing into more advanced technology nodes are desperate to understand what’s driving their yield,” says Ronald Chaffee, senior director of applications engineering at NI/Emerson Test & Measurement. “They may not know what all the issues are, but they are gathering all possible data — metrology, AEOI, and any measurable parameters — and seeking correlations.”

Traditional methods for defect detection, pattern recognition, and quality control typically used spatial pattern-recognition modules and wafer image-based algorithms to address wafer-level issues. “However, we need to advance beyond these techniques,” says Prasad Bachiraju, senior director of business development at Onto Innovation. “Our observations show that about 20% of wafers have systematic issues that can limit yield, with nearly 4% being new additions. There is a pressing need for advanced metrology for in-line monitoring to achieve zero-defect manufacturing.”

Several companies recently announced metrology innovations to provide more precise inspections, particularly for difficult-to-see areas, edge effects, and highly reflective surfaces.

Nordson unveiled its AMI SpinSAM acoustic rotary scan system. The system represents a significant departure from traditional raster scan methods, utilizing a rotational scanning approach. Rather than moving the wafer in an x,y pattern relative to a stationary lens, the wafer spins, similar to a record player. This reduces motion over the wafer and increases inspection speed, negating the need for image stitching and improving image quality.

“For years, we’d been trying to figure out this technique, and it’s gratifying to finally achieve it. It’s something we’ve always thought would be incredibly beneficial,” says Perkins. “The SpinSAM is designed primarily to enhance inspection speed and efficiency, addressing the common industry demand for more product throughput and better edge inspection capabilities.”

Meanwhile, Nearfield Instruments introduced a multi-head atomic force microscopy (AFM) system called QUADRA. It is a high-throughput, non-destructive metrology tool for HVM that features a novel multi-miniaturized AFM head architecture. Nearfield claims the parallel independent multi-head scanner can deliver a 100-fold throughput advantage versus conventional single-probe AFM tools. This architecture allows for precise measurements of high-aspect-ratio structures and complex 3D features, critical for advanced memory (3D NAND, DRAM, HBM) and logic processes.

Fig. 1: Image capture comparison of standard AFM and multi-head AFM. Source: Nearfield Instruments

In April, Onto Innovation debuted an advancement in subsurface defect inspection technology with the release of its Dragonfly G3 inspection system. The new system allows for 100% wafer inspection, targeting subsurface defects that can cause yield losses, such as micro-cracks and other hidden flaws that may lead to entire wafers breaking during subsequent processing steps. The Dragonfly G3 utilizes novel infrared (IR) technology combined with specially designed algorithms to detect these defects, which previously were undetectable in a production environment. This new capability supports HBM, advanced logic, and various specialty segments, and aims to improve final yield and cost savings by reducing scrapped wafers and die stacks.

More recently, researchers at the Paul Scherrer Institute announced a high-performance X-ray tomography technique using burst ptychography. This new method can provide non-destructive, detailed views of nanostructures as small as 4nm in materials like silicon and metals at a fast acquisition rate of 14,000 resolution elements per seconds. The tomographic back-propagation reconstruction allows imaging of samples up to ten times larger than the conventional depth of field.

There are other technologies and techniques for improving metrology in semiconductor manufacturing, as well, including wafer-level ultrasonic inspection, which involves flipping the wafer to inspect from the other side. New acoustic microscopy techniques, such as scanning acoustic microscopy (SAM) and time-of-flight acoustic microscopy (TOF-AM), enable the detection and characterization of very small defects, such as voids, delaminations, and cracks within thin films and interfaces.

“We used to look at 80 to 100 micron resist films, but with 3D integrated packaging, we’re now dealing with films that are 160 to 240 microns—very thick resist films,” says Christopher Claypool, senior application scientist at Bruker OCD. “In TSVs and microbumps, the dominant technique today is white light interferometry, which provides profile information. While it has some advantages, its throughput is slow, and it’s a focus-based technique. This limitation makes it difficult to measure TSV structures smaller than four or five microns in diameter.”

Acoustic metrology tools equipped with the newest generation of focal length transducers (FLTs) can focus acoustic waves with precision down to a few nanometers, allowing for non-destructive detailed inspection of edge defects and critical stress points. This capability is particularly useful for identifying small-scale defects that might be missed by other inspection methods.

The development and integration of smart sensors in metrology equipment is instrumental in collecting the vast amounts of data needed for precise measurement and quality control. These sensors are highly sensitive and capable of operating under various environmental conditions, ensuring consistent performance. One significant advantage of smart sensors is their ability to facilitate predictive maintenance. By continuously monitoring the health and performance of metrology equipment, these sensors can predict potential failures and schedule maintenance before significant downtime occurs. This capability enhances the reliability of the equipment, reduces maintenance costs, and improves overall operational efficiency.

Smart sensors also are being developed to integrate seamlessly with metrology systems, offering real-time data collection and analysis. These sensors can monitor various parameters throughout the manufacturing process, providing continuous feedback and enabling quick adjustments to prevent defects. Smart sensors, combined with big data platforms and advanced data analytics, allow for more efficient and accurate defect detection and classification.

Critical stress points

A persistent challenge in semiconductor metrology is the identification and inspection of defects at critical stress points, particularly at the silicon edges. For bonded wafers, it’s at the outer ring of the wafer. For chip-on-wafer packaging, it’s at the edge of the chips. These edge defects are particularly problematic because they occur at the highest stress points from the neutral axis, making them more prone to failures. As semiconductor devices continue to involve more intricate packaging techniques, such as chip-on-wafer and wafer-level packaging, the focus on edge inspection becomes even more critical.

“When defects happen in a factory, you need imaging that can detect and classify them,” says Onto’s Bachiraju. “Then you need to find the root causes of where they’re coming from, and for that you need the entire data integration and a big data platform to help with faster analysis.”

Another significant challenge in semiconductor metrology is ensuring the reliability of known good die (KGD), especially as advanced packaging techniques and chiplets become more prevalent. Ensuring that every chip/chiplet in a stacked die configuration is of high quality is essential for maintaining yield and performance, but the speed of metrology processes is a constant concern. This leads to a balancing act between thoroughness and efficiency. The industry continuously seeks to develop faster machines that can handle the increasing volume and complexity of inspections without compromising accuracy. In this race, innovations in data processing and analysis are key to achieving quicker results.

“Customers would like, generally, 100% inspection for a lot of those processes because of the known good die, but it’s cost-prohibitive because the machines just can’t run fast enough,” says Nordson’s Perkins.

Metrology and Industry 4.0

Industry 4.0 — a term introduced in Germany in 2011 for the fourth industrial revolution, and called smart manufacturing in the U.S. — emphasizes the integration of digital technologies such as the Internet of Things, artificial intelligence, and big data analytics into manufacturing processes. Unlike past revolutions driven by mechanization, electrification, and computerization, Industry 4.0 focuses on connectivity, data, and automation to enhance manufacturing capabilities and efficiency.

“The better the data integration is, the more efficient the yield ramp,” says Dieter Rathei, CEO of DR Yield. “It’s essential to integrate all available data into the system for effective monitoring and analysis.”

In semiconductor manufacturing, this shift toward Industry 4.0 is particularly transformative, driven by the increasing complexity of semiconductor devices and the demand for higher precision and yield. Traditional metrology methods, heavily reliant on manual processes and limited automation, are evolving into highly interconnected systems that enable real-time data sharing and decision-making across the entire production chain.

“There haven’t been many tools to consolidate different data types into a single platform,” says NI’s Chaffee. “Historically, yield management systems focused on testing, while FDC or process systems concentrated on the process itself, without correlating the two. As manufacturers push into the 5, 3, and 2nm spaces, they’re discovering that defect density alone isn’t the sole governing factor. Process control is also crucial. By integrating all data, even the most complex correlations that a human might miss can be identified by AI and ML. The goal is to use machine learning to detect patterns or connections that could help control and optimize the manufacturing process.”

IoT forms the backbone of Industry 4.0 by connecting various devices, sensors, and systems within the manufacturing environment. In semiconductor manufacturing, IoT enables seamless communication between metrology tools, production equipment, and factory management systems. This interconnected network facilitates real-time monitoring and control of manufacturing processes, allowing for immediate adjustments and optimization.

“You need to integrate information from various sources, including sensors, metrology tools, and test structures, to build predictive models that enhance process control and yield improvement,” says Michael Yu, vice president of advanced solutions at PDF Solutions. “This holistic approach allows you to identify patterns and correlations that were previously undetectable.”

AI and ML are pivotal in processing and analyzing the vast amounts of data generated in a smart factory. These technologies can identify patterns, predict equipment failures, and optimize process parameters with a level of precision and speed unattainable by human operators alone. In semiconductor manufacturing, AI-driven analytics enhance process control, improve yield rates, and reduce downtime. “One of the major trends we see is the integration of artificial intelligence and machine learning into metrology tools,” says Perkins. “This helps in making sense of the vast amounts of data generated and enables more accurate and efficient measurements.”

AI’s role extends further as it assists in discovering anomalies within the production process that might have gone unnoticed with traditional methods. AI algorithms integrated into metrology systems can dynamically adjust processes in real-time, ensuring that deviations are corrected before they affect the end yield. This incorporation of AI minimizes defect rates and enhances overall production quality.

“Our experience has shown that in the past 20 years, machine learning and AI algorithms have been critical for automatic data classification and die classification,” says Bachiraju. “This has significantly improved the efficiency and accuracy of our metrology tools.”

Big data analytics complements AI/ML by providing the infrastructure necessary to handle and interpret massive datasets. In semiconductor manufacturing, big data analytics enables the extraction of actionable insights from data generated by IoT devices and production systems. This capability is crucial for predictive maintenance, quality control, and continuous process improvement.

“With big data, we can identify patterns and correlations that were previously impossible to detect, leading to better process control and yield improvement,” says Perkins.

Big data analytics also helps in understanding the lifecycle of semiconductor devices from production to field deployment. By analyzing product performance data over time, manufacturers can predict potential failures and enhance product designs, increasing reliability and lifecycle management.

“In the next decade, we see a lot of opportunities for AI,” says DR Yield’s Rathei. “The foundation for these advancements is the availability of comprehensive data. AI models need extensive data for training. Once all the data is available, we can experiment with different models and ideas. The ingenuity of engineers, combined with new tools, will drive exponential progress in this field.”

Metrology gaps remain

Despite recent advancements in metrology, analytics, and AI/ML, several gaps still remain, particularly in the context of high-volume manufacturing (HVM) and next-generation devices. The U.S. Commerce Department’s CHIPS R&D Metrology Program, along with industry stakeholders, have highlighted seven “grand challenges,” areas where current metrology capabilities fall short:

Metrology for materials purity and properties: There is a critical need for new measurements and standards to ensure the purity and physical properties of materials used in semiconductor manufacturing. Current techniques lack the sensitivity and throughput required to detect particles and contaminants throughout the supply chain.

Advanced metrology for future manufacturing: Next-generation semiconductor devices, such as gate-all-around (GAA) FETs and complementary FETs (CFETs), require breakthroughs in both physical and computational metrology. Existing tools are not yet capable of providing the resolution, sensitivity, and accuracy needed to characterize the intricate features and complex structures of these devices. This includes non-destructive techniques for characterizing defects and impurities at the nanoscale.

“There is a secondary challenge with some of the equipment in metrology, which often involves sampling data from single points on a wafer, much like heat test data that only covers specific sites,” says Chaffee. “To be meaningful, we need to move beyond sampling methods and find creative ways to gather information from every wafer, integrating it into a model. This involves building a knowledge base that can help in detecting patterns and correlations, which humans alone might miss. The key is to leverage AI and machine learning to identify these correlations and make sense of them, especially as we push into the 5, 3, and 2nm spaces. This process is iterative and requires a holistic approach, encompassing various data points and correlating them to understand the physical boundaries and the impact on the final product.”

Metrology for advanced packaging: The integration of sophisticated components and novel materials in advanced packaging technologies presents significant metrology challenges. There is a need for rapid, in-situ measurements to verify interfaces, subsurface interconnects, and internal 3D structures. Current methods do not adequately address issues such as warpage, voids, substrate yield, and adhesion, which are critical for the reliability and performance of advanced packages.

Modeling and simulating semiconductor materials, designs, and components: Modeling and simulating semiconductor processes require advanced computational models and data analysis tools. Current capabilities are limited in their ability to seamlessly integrate the entire semiconductor value chain, from materials inputs to system assembly. There is a need for standards and validation tools to support digital twins and other advanced simulation techniques that can optimize process development and control.

“Predictive analytics is particularly important,” says Chaffee. “They aim to determine the probability of any given die on a wafer being the best yielding or presenting issues. By integrating various data points and running different scenarios, they can identify and understand how specific equipment combinations, sequences and processes enhance yields.”

Modeling and simulating semiconductor processes: Current capabilities are limited in their ability to seamlessly integrate the entire semiconductor value chain, from materials inputs to system assembly. There is a need for standards and validation tools to support digital twins and other advanced simulation techniques that can optimize process development and control.

“Part of the problem comes from the back-end packaging and assembly process, but another part of the problem can originate from the quality of the wafer itself, which is determined during the front-end process,” says PDF’s Yu. “An effective ML model needs to incorporate both front-end and back-end information, including data from equipment sensors, metrology, and structured test information, to make accurate predictions and take proactive actions to correct the process.”

Standardizing new materials and processes: The development of future information and communication technologies hinges on the creation of new standards and validation methods. Current reference materials and calibration services do not meet the requirements for next-generation materials and processes, such as those used in advanced packaging and heterogeneous integration. This gap hampers the industry’s ability to innovate and maintain competitive production capabilities.

Metrology to enhance security and provenance of components and products: With the increasing complexity of the semiconductor supply chain, there is a need for metrology solutions that can ensure the security and provenance of components and products. This involves developing methods to trace materials and processes throughout the manufacturing lifecycle to prevent counterfeiting and ensure compliance with regulatory standards.

“The focus on security and sharing changes the supplier relationship into more of a partnership and less of a confrontation,” says Chaffee. “Historically, there’s always been a concern of data flowing across that boundary. People are very protective about their process, and other people are very protective about their product. But once you start pushing into the deep sub-micron space, those barriers have to come down. The die are too expensive for them not to communicate, but they can still do so while protecting their IP. Companies are starting to realize that by sharing parametric test information securely, they can achieve better yield management and process optimization without compromising their intellectual property.”

Conclusion

Advancements in metrology and testing are pivotal for the semiconductor industry’s continued growth and innovation. The integration of AI/ML, IoT, and big data analytics is transforming how manufacturers approach process control and yield improvement. As adoption of Industry 4.0 grows, the role of metrology will become even more critical in ensuring the efficiency, quality, and reliability of semiconductor devices. And by leveraging these advanced technologies, semiconductor manufacturers can achieve higher yields, reduce costs, and maintain the precision required in this competitive industry.

With continuous improvements and the integration of smart technologies, the semiconductor industry will keep pushing the boundaries of innovation, leading to more robust and capable electronic devices that define the future of technology. The journey toward a fully realized Industry 4.0 is ongoing, and its impact on semiconductor manufacturing undoubtedly will shape the future of the industry, ensuring it stays at the forefront of global technological advancements.

“Anytime you have new packaging technologies and process technologies that are evolving, you have a need for metrology,” says Perkins. “When you are ramping up new processes and need to make continuous improvements for yield, that is when you see the biggest need for new metrology solutions.”

The post Metrology And Inspection For The Chiplet Era appeared first on Semiconductor Engineering.

With highly competitive time-to-market and time-to-volume windows, IC suppliers need to be able to release new product to production (NPI) in a timely manner with competitive manufacturing metrics. Manufacturing yield, test time and quality are important metrics in NPI to Manufacturing safe launch. A powerful yield management system is crucial to achieve the goal metrics. In this paper, recommended yield management system selection criteria, data integration methodology and innovative ways of using selected yield management system to benefit safe launch efficiency are introduced. Three examples of using cloud yield tool to expedite yield learning, test time reduction (TTR) and quality enhancement are presented.

Find more information here.

The post Expediting Manufacturing Safe Launch With Big Data AI/ML Analytic Solutions On The Cloud appeared first on Semiconductor Engineering.

Everybody has several games that mean quite a lot to them. For me, one of these games is Indiana Jones and the Infernal Machine. I not only grew up with this game, but I also have a lot of memories of this game. Outside of that, I also met some amazing friends through the community behind this game. I even did several speedruns of this game, and I’m an active member of the community. Now, color me surprised that 25 years after the release of this game, we got new fan-made content for this game. Not just fan made content in the style of fan patches to solve bugs with the game, a whole new level and promises of a level editor to create even more new custom content. This blew me off my socks and in today’s article I want to talk about it. So strap in and let’s get ready to play new content for one of the best Indiana Jones games ever made.

The new level – SED

There is a speedrunning discord server for this game. Well, it was a speedrunning discord server but for a few years now, this server has grown into a server of people who appreciate this game. If you want to join this discord, here is an invite link. When the server started to grow, several modders joined our server. One of these modders is going under the name of Urgon (currently) and what we didn’t know is that he was decompiling the whole game. Not only that, he was creating a level editor based upon an existing level editor.

This existing level editor is for Star Wars Jedi Knight & Mysteries of the Sith. Those games used an engine that formed the basis for the Jones3D engine. While he was developing that editor, he tested his skills by creating a new level. So, basically, parts of this new level are tests of the new level editor and what you can do with it.

Now, information about this new level and the download link can be found at this GitHub repository. If you want to download the actual level, you have to go to this page and click the green button named “Code”. In that dropdown, you can choose “download zip”. You’ll need that later if you want to install/play this custom level. Now, if you read the pre-mod or the installation instructions for this level, you might feel overwhelmed if you aren’t very technically inclined. That’s why two community members wrote two special tools to aid you in preparing your game.

You might ask yourself, like Klamath did in at the end of our stream of this custom level, why are there two tools for basically the same? Well, let me tell you the history about it. When I wanted to play the custom level, I had a bit of trouble myself while figuring out the tutorial. I also found that the required steps were quite a lot to do. So, I decided to start writing a PowerShell script that did all the steps. I announced that in the Indy3D discord that I was writing this. When I almost completed my tool, the_Kovic dropped his version of the tool.

Personally, I didn’t want to throw my work out the window and continued finishing my GUI version. When I finished, I didn’t convert my tool to an EXE and left it just as a script file you could run using a command line or a code editor. The next day, Kovic released a GUI version of his tool and I gave some feedback on his tool. In the days after that, I created an EXE version of my tool and we both kept adding features in our tool. He wrote his tool in C#, which is a bit friendlier to create an EXE. If I didn’t release my first version as a script only and converted it to an EXE, I think it might have been less overwhelming for people.

That said, Kovic thanked me for creating my tool since like he said on our stream: “It put my butt into gear to create a tool and write a GUI, which I normally don’t write“. On top of that, our tools aren’t meant to compete with each other. I can’t write C# and Kovic can’t write PowerShell. And it would be a shame to just delete work because somebody else was quicker or made their tool more user-friendly first. The result now is that we both have two very strong tools with a very similar, maybe even completely the same, feature set.

Outside a different choice of coding language, the biggest differences between both our tools are under the hood. In Kovic’s tool, you get more files than in my tool when you download the tool. And that’s because to prepare your game for custom levels, you need to extract several files in the resource folder. The tool used for extraction has a bug where instead of extracting the folders of the archive into the resource folder, it extracts them into separate folders, like if you would extract a zip file. Kovic packs a modified version of this extraction tool so that part of the process goes a bit faster. In my version, the tool just downloads the latest official versions of the tool and prepare the game that way.

In the end, both our tools give you the same end result. They prepare your game to install custom levels and play them. If you want to try out the_kovic’s tool, you can find the latest version on this releases page. If you want to try our my tool, you can find it on this releases page. Feedback to our tools is always welcome! If you find an issue or if you have an idea, feel free to hit us up, and we will look into it.

Earlier I talked about a stream of the level we did. Klamath, the_Kovic and me did a live stream where we played through this level. Now, I have to emphasize that release of this level is an impressive technical achievement. Creating a level for a 3D game isn’t easy and requires a lot of work. It’s even more impressive when you know that not everything is documented about the engine, and you have to decompile a lot of it. In the next part of this article, I’m going to talk about the level itself and critique it.

If you don’t want spoilers, I’d advise you to skip that section for now and come back later. Now, I want to say that I start reviewing the level in a moment, but this feedback is mostly meant for people who want to make new custom content. What did this new level do right and wrong if you look at it as a player who doesn’t know the technical background of this level? This isn’t meant to break down the amazing work the modders did to make this work.

Reviewing the new level

Editorial note: this review will spoil quite a lot. If you don’t want to get spoiled, you have to skip this section of the article. This isn’t a walkthrough of the level either. Some sections are skipped, I’m only going to talk about the sections I want to talk about.

The new level takes place 25 years after the ending of the original game. Indy returns to his Canyonlands dig site. You are set loose at the tent where Sophia picked Indy up with a helicopter to start the Infernal Machine adventure.

In terms of new content, there isn’t a lot new to see. Some ladders are missing and some parts of the level are blocked off. Also, all treasures are missing that you would usually find in the level.

Before I continue, I want to mention that some parts of this level are made quite difficult on purpose. The developer wanted to give us the feeling we were young kids again, playing this game for the first time, and have us figure out the new puzzles by ourselves. Yet, finding a correct balance between difficulty and unfair is a very fine line to thread. Personally, I think that in some sections, the developer crossed the line into unfair level design.

When running on the top section, you notice that there are some new voice lines. These voice lines are made possible with a voice cloning AI tool that was trained on lines from Doug Lee, the original voice actor for this game. The new voice lines sound amazing, and if you didn’t know better, you’d think that Doug Lee came back to record the new lines. In most cases, these voice lines really fit Indy’s personality and fit right into the game.

We come to our first snag when we want to go to the new content. I can understand not seeing the shovel and being confused, since it’s hanging at the jeep on top. And you know what’s even more confusing, the other side of the jeep model has a shovel in its texture! Anyhow, when you pick up the shovel and dig up the Infernal Machine part, it’s clear that you need to break a wall. Here comes one of the worst parts of this level. The location of this cracked wall is insanely well hidden. It’s in one of the last places you’d look, and several of the first players ran around for hours upon hours in Canyonlands before it was found. And when it was found, it made us annoyed.

It’s a clear example of how players who are used to the level, overlooking the obvious. The wall you need to break has an actual cracked wall texture, but it’s behind something you can’t see through. I think it would have been fine if the location, where it is at, had a bigger ledge so you’d notice it somewhat instead of just having to go on a wild goose chase.

Now, we enter the new area. We come to a big open space where the next set of puzzles are. The first puzzle is actually a jumping puzzle. Now, I highly advise you to not play this level if you haven’t played through most of Indiana Jones and the Infernal Machine. Not that there are spoilers, but because some of the jumps in this level are straight up difficult and not what you really expect from this game. Kovic calls it “Kaizo Jones” for a good reason.

There are some small platforms and not having the look key working is going to be a pain in this section. Since, there are some moments where you need to be able to free look and not being able to see beneath or above you will make things a lot more tricky. After you finished these jumps, you might start to notice that the developer of this custom level added some details. Like, the rope bridges are gently moving in the wind. This is something that isn’t present in the original game. It’s a new “COG” script that makes that possible.

These cog scripts are a blessing for custom content. Since, this game isn’t hardcoded at all, so if you learn how to write these cog scripts, you can basically write new mechanics as well. It’s insane what possibilities there are going to be in the future for this game. I hope there is going to be good documentation so that custom level creaters know what’s possible and what’s impossible with the level editor.

While you are exploring this area, you notice that it’s huge. This also explains why it takes quite a while to load this level. Currently, modders are looking into why it’s running so slow. Since, we don’t really know if it’s the level size or something else slowing down the loading of this level.

So, after jumping around the central column, you’ll arive at the shed. Here you notice you can actually enter the shed from the top. Kovic explains it quite well during the stream. If you want to hear some technical explanations on how this level works, I’d advice you to watch our stream. Since there is a lot of interesting development talk in there. Later, Kovic and myself had a contest in trying to quote voice lines from the main game. We got close to 200. Kovic won that because I said a line he already said.

After you picked up everything from this shed and climbed outside, you experience another new mechanic of this game. It’s a mechanic that gets backported from Indiana Jones and the Emperor’s Tomb. The fact you can use your whip to go over a zipline.

After you returned and struggled with getting across the other bridge, you will encounter other parts of this level. Here you’ll encounter two voice lines that straight up lie to you. The first voice line is that you need more force, explosives to break a rock that’s blocking your way forwards. Here is the issue with that, you get an explosive barrel later. You need to find an extremely hidden swim tunnel in the water. It’s not the only hidden thing in the water, so investigate behind and underneath rocks quite well. Since, these puzzles in this water border in the unfair territory. What makes that explosive voice line even more evil is that there is a box of TNT in the shed earlier. But what’s the second voice line that lies to you?

Well, that is after you made your way past said boulder. You find a minecart and interacting with it, Indy says that it will run with gasoline. And there is still gasoline left in the shed. Sadly, you can’t pick it up anymore. Now, this is a red haring, you don’t need this minecart at all.

By now, you have learned that this level likes to break the rules of how the main game is designed. You’ll have to think outside of the box sometimes to beat this level. But, for some jumps, you need to use your knowledge of what’s possible and impossible to progress. This makes it quite tricky sometimes to progress. And this brings me to a conclusion we also said on stream. I think that the issue is that people expected a more tame level than what we actually got and that might turn some people off. But, I’m so glad that the quick save system exists in this game. So, abuse the quick save system and make multiple saves since you’ll need them if you aren’t a veteran player of this game.

Anyhow, let’s get back into the flow of the level. After we completed the lever puzzle, we go back towards to the huge open area and take the lift to a new location. What follows is a totally new area where it’s a good thing if you saved up on health packs and you have a great sense of direction.

So, the short minecart ridge comes to an end. It doesn’t take long before you find yourself into a watermaze. This watermaze is unfair in my honest opinion. Klamath had a tricky time solving it and he had to use almost every health pack to get through it. Without Kovic pointing out the right tunnel, I think it would have made the stream quite a bit longer. There was supposed to be a minecart section instead of this swimming maze, but the developer had a hard time making the minecart section to work and he gave up and made this swimming maze.

Now, I’m all fine with this swimming maze, but the map glitches out at certain parts. I have a mediocre sense of direction and I wanted to rely on the map. The map doesn’t always render the tunnels correctly. You sometimes swim off the map or “in nothingness”. Sadly, I have to draw my own map. I wish I still had it, since it would make for a nice screenshot here… But I threw it out but me and my clumsiness… I knocked over my waterbottle over it.

After the swimming maze, we get a new section of “Kaizo Jones”. Where we get some extremely tricky platforming. Here is where you need to use the look key again and be sure you are playing in 4:3. If you are playing in another resolution like 16:9 or 16:10, this will also be one of the moments where you don’t see all the information.

The block puzzle that follows, feels right out of Tomb Raider. The initial reviews of this game called out this game as a Tomb Raider clone. While, this game does the formula a whole lot differently. We even talked about that during the stream. In terms of theming, Infernal Machine is a lot better. Tomb Raider feels like obstacle courses. But that’s thanks to a different engine and control style. If you want to hear the whole discussion, you can watch the stream from this point. Excuse Kovic’s internet being spotty while he was replying.

After the block puzzle, a new path opens in the swim maze. Then, some platforming comes. Something I love is how there is even a troll hidden inside the platforming. It caught me off guard and made me smile. This platforming section was also love to do. It felt like a real test on how well I know the game. This platforming section feels a lot better put together and feel less cryptic on where you need to go next. You really start to notice that the developer was getting more used to the level editor and made better puzzles. The moment of having to use the whip to swing over the gap while the platform underneath you was breaking was amazing.

After that, we get into the finale of this level. We jump into a portal and we land in a playable area which is shown at the end of Shambala, the 4th level in the original game. That area that’s shown to you after you have beaten the Ice Guardian. The path that takes you to Palawan Lagoon. It was possible to explore that using cheats and modified saves, but now it’s in a level for real. Exploring the little house at the end brings us to something you totally don’t expect this custom level to do. You’ll find a parchment inside with a riddle and at the end you notice something in red saying: “MAT -> ZIP”.

There is some meta gaming now going on. You’ll need to make a hard save and exit your game. You’ll need to go to your resource folder & then open the MAT folder. In there you’ll need to rename “SED.MAT” to “SED.ZIP”. You’ll also need to enter the password for the zip, since you get a new cog script to continue the level, which you need to place in your cog folder. In there, there is another surprise. But, that’s something I’m not going to spoil. But, be sure that Kovic is playing with that surprise and maybe I’m going to dig into it. PS, the next paragraph is in white with the right spelling of the password:

Marcus

The way the level ends is bittersweet. If you solve the final puzzle, something special happens and you can beat the level. You could argue that the ending of this level is “lazy” or “creative”… But, it’s an amazing way to wrap up the story in one level with a nice bow.

At the start of the custom level, I felt that it was quite rough around the edges and it had some moments that felt badly designed. In terms of game design that is. If you look at it visually and level flow wise, I personally think that this level would fit right into the original game as a final challenge. But, the further you go into the level, the more you start to notice that the developer of this level is getting used to the tools and the editor and more polished puzzles and area’s are coming through. You notice the journey of the developer and see it becoming better and better.

I want to give a big congrats to everybody who was involved in releasing this custom level. It’s a blast to play and I can’t wait to see more custom levels. The stream I did with this level was one of the best streams ever and it was also quite a lot of fun to write the tool to help people play this custom level. I’m curious what you think about this custom level and/or the content of this article. Feel free to drop something in the comment section down below.

And with that, I have said everything I wanted to say about this for now. I want to thank you so much for reading and I hope you enjoyed it as much as I enjoyed writing it. I hope to welcome you back in another article but until then, have a great rest of your day and take care.

One of the big challenges for IC test is making sense of mountains of data, a direct result of more features being packed onto a single die, or multiple chiplets being assembled into an advanced package. Collecting all that data through various agents and building models on the tester no longer makes sense for a couple reasons — there is too much data, and there are multiple customers using the same equipment. Steve Zamek, director of product management at PDF Solutions, and Eli Roth, product manager at Teradyne, explain how to optimize testing around different data sources, how to partition that data between the edge and the cloud, and how to ensure it remains secure.

The post Making Adaptive Test Work Better appeared first on Semiconductor Engineering.

The need to mitigate climate change is driving a need to electrify our infrastructure, vehicles, and appliances, which can then be charged and powered by renewable energy sources. The most visible and impactful electrification is now under way for electric vehicles (EVs). Beyond the transition to electric engines, several new features and technologies are driving the electrification of vehicles. The number of sensors in a vehicle is skyrocketing, driven by autonomous driving and other safety features, while a modern software-defined vehicle (SDV) is electrifying everything from air-conditioned seats to self-parking technology.

An important technology for EVs and SDVs is power modules. These are super high-voltage devices that convert one form of electricity to another (e.g., AC to DC), which is necessary to convert the vehicle battery energy to a current that can run the vehicles electrical system, including the drive train. These modules demand the highest power loads and are rated at 1000s of voltages – and the design of power devices, which are the fundamental electronic component of the power modules, is crucial, as a bad design can lead to catastrophe events.

Power devices, much more than other types of electrical devices, are designed for specific applications. In comparison, logic transistors can be used in everything from toasters to smartphones. Not only does the architecture of power devices change at higher voltages, different power ratings, or higher switching frequencies as needed, but the material can change as well.

New power requirements need wide-band gap materials

To meet new and future power demands for EVs, electric infrastructure, and other novel electrical systems, wide-band gap (WBG) materials are being developed and introduced. Silicon carbide (SiC) IGBTs are now available and being deployed, while gallium arsenide (GaN) HEMTs are a promising technology that is in the development stage.

Power density vs. switching frequency of power devices based on different materials.

Continuing with our EV example, SiC inverters can generally increase the potential range by approximately 10%, even after accounting for other design considerations. In addition, increasing the drive train voltage from 400V range to 800V can reduce the charging speeds by half. These voltages are only possible to realize with wide-band gap materials like SiC-based power devices. Tesla introduced SiC MOSFETs into its Model S back in 2018. Since then, numerous automotive manufacturers have also adopted SiC in their EVs, including Hyundai and BMW, for example.

GaN still has many design hurdles to overcame to improve reliability and decrease cost – but if it can be made affordable, perhaps the next realization of EVs will allow for charging in seconds with ranges of thousands of miles.

Simulating power devices

Because of the huge number of design parameters, simulation is important in the design of power devices. One crucial part for device design is the calculation of the breakdown voltage – the voltage at which the device can essentially melt, or catch fire, but will never operate again. These simulations need to be highly physics-based and capture the mechanisms by which electrons can be released or absorbed by the crystal lattice of these materials. The increasing band gaps in WBG materials like SiC and GaN increase the breakdown voltage. In addition, these materials have a smaller effective electron mass (i.e., the mass of an electron in a material dictates how fast it will move in an electric field) – which makes the switching frequency in devices based on these WBG materials faster.

A critical area of all electronics design is variability and reliability. Device performance needs to be stable and last a long time. A key factor for variability and reliability is defects in the crystal lattice. These defects, or traps, act as charge centers that can drastically impact how well a device works. Simulation can also help to identify the types of traps, providing a mechanistic understanding of how the traps will impact the device physics. Recently, Synopsys issued a paper using first-principles quantum solutions to characterize specific traps in SiC with QuantumATK.

Going forward, wind energy, solar, home appliances, and even the electric grid itself are going to need new devices with different structures and materials. The future is extremely exciting for power devices, which can be found in our EVs and will soon power a huge range of applications across our society.

The post Enabling New Applications With SiC IGBT And GaN HEMT For Power Module Design appeared first on Semiconductor Engineering.

The need to mitigate climate change is driving a need to electrify our infrastructure, vehicles, and appliances, which can then be charged and powered by renewable energy sources. The most visible and impactful electrification is now under way for electric vehicles (EVs). Beyond the transition to electric engines, several new features and technologies are driving the electrification of vehicles. The number of sensors in a vehicle is skyrocketing, driven by autonomous driving and other safety features, while a modern software-defined vehicle (SDV) is electrifying everything from air-conditioned seats to self-parking technology.

An important technology for EVs and SDVs is power modules. These are super high-voltage devices that convert one form of electricity to another (e.g., AC to DC), which is necessary to convert the vehicle battery energy to a current that can run the vehicles electrical system, including the drive train. These modules demand the highest power loads and are rated at 1000s of voltages – and the design of power devices, which are the fundamental electronic component of the power modules, is crucial, as a bad design can lead to catastrophe events.

Power devices, much more than other types of electrical devices, are designed for specific applications. In comparison, logic transistors can be used in everything from toasters to smartphones. Not only does the architecture of power devices change at higher voltages, different power ratings, or higher switching frequencies as needed, but the material can change as well.

New power requirements need wide-band gap materials

To meet new and future power demands for EVs, electric infrastructure, and other novel electrical systems, wide-band gap (WBG) materials are being developed and introduced. Silicon carbide (SiC) IGBTs are now available and being deployed, while gallium arsenide (GaN) HEMTs are a promising technology that is in the development stage.

Power density vs. switching frequency of power devices based on different materials.

Continuing with our EV example, SiC inverters can generally increase the potential range by approximately 10%, even after accounting for other design considerations. In addition, increasing the drive train voltage from 400V range to 800V can reduce the charging speeds by half. These voltages are only possible to realize with wide-band gap materials like SiC-based power devices. Tesla introduced SiC MOSFETs into its Model S back in 2018. Since then, numerous automotive manufacturers have also adopted SiC in their EVs, including Hyundai and BMW, for example.

GaN still has many design hurdles to overcame to improve reliability and decrease cost – but if it can be made affordable, perhaps the next realization of EVs will allow for charging in seconds with ranges of thousands of miles.

Simulating power devices

Because of the huge number of design parameters, simulation is important in the design of power devices. One crucial part for device design is the calculation of the breakdown voltage – the voltage at which the device can essentially melt, or catch fire, but will never operate again. These simulations need to be highly physics-based and capture the mechanisms by which electrons can be released or absorbed by the crystal lattice of these materials. The increasing band gaps in WBG materials like SiC and GaN increase the breakdown voltage. In addition, these materials have a smaller effective electron mass (i.e., the mass of an electron in a material dictates how fast it will move in an electric field) – which makes the switching frequency in devices based on these WBG materials faster.

A critical area of all electronics design is variability and reliability. Device performance needs to be stable and last a long time. A key factor for variability and reliability is defects in the crystal lattice. These defects, or traps, act as charge centers that can drastically impact how well a device works. Simulation can also help to identify the types of traps, providing a mechanistic understanding of how the traps will impact the device physics. Recently, Synopsys issued a paper using first-principles quantum solutions to characterize specific traps in SiC with QuantumATK.

Going forward, wind energy, solar, home appliances, and even the electric grid itself are going to need new devices with different structures and materials. The future is extremely exciting for power devices, which can be found in our EVs and will soon power a huge range of applications across our society.

The post Enabling New Applications With SiC IGBT And GaN HEMT For Power Module Design appeared first on Semiconductor Engineering.

The challenges before semiconductor fabs are expansive and evolving. As the size of chips shrinks from nanometers to eventually angstroms, the complexity of the manufacturing process increases in response. It can take hundreds of process steps and more than a month to process a single wafer. It can subsequently take more than another month to go through the assembly, testing, and packaging steps necessary to get to the final product.

Artificial Intelligence (AI) can be deployed within a fab to address the complexity and intricacy of semiconductor manufacturing. A fab generates petabytes of data as wafers go through the multitude of process and test operations. This wealth of data also presents a challenge in that it needs to be analyzed and acted on quickly to ensure tight process control, high yield, and avoid process excursions. Beyond navigating the complexity of the manufacturing process, new solutions are necessary to help make the process as efficient as possible and the yield as high as possible to produce the most business value for fabs.

The benefits of AI-enabled analysis tools for IC manufacturers

Traditional techniques to detect issues in the manufacturing process have run out of steam, especially at advanced technology nodes. For example, an engineer must do their own yield analysis to seek out potential problems. Once they identify an issue, they communicate with the defect and process teams to determine the root cause and then troubleshoot it. The defect team will begin work to find some correlation behind the issue and the process team troubleshoot and link it to the root cause.

All these steps take up significant time that could be focused on achieving the highest yield of chips possible, driving costs down and reducing time to market. One of the biggest benefits of enabling AI in analysis tools is that an engineer can quickly recognize and pinpoint an issue in a specific chip to see which process step and/or equipment has caused the issue.

Beyond the fast and accurate process control that AI allows for, there are numerous other benefits that result from the saved time and money, including:

• Predictive applications: Enables fabs to take leap from reactive to predictive process control
• Scalability: Analyzes petabytes of data, connects multiple fabs, and comes cloud-ready
• Efficiency: Allows fab to make better decisions and reduce false alarms

To enable the next generation of manufacturing, Synopsys is enabling AI and Machine Learning (ML) for a comprehensive process control solution.

Actionable insights with AI and ML

Wafer, equipment, design, mask, test, and yield are silos within a fab that can benefit from a comprehensive AI/ML enabled solution. Such a solution can specifically help engineers generate actionable insights into the following:

• Fault detection and classification (FDC)
• Statistical process control (SPC)
• Dynamic fault detection (DFD)
• Defect classification and image analytics
• Defect image analytics
• Decision support system (DSS)

Fast analysis of petabytes of data, from equipment sensors or process parameters, allows manufacturers to quickly identify the root cause of process excursions and take action to maintain yield.

AI and ML in the fab

Synopsys is a provider of software solutions for silicon manufacturing and silicon lifecycle management, including solutions for TCAD, mask solutions, and manufacturing analytics. Its existing solutions are connected to thousands of pieces of equipment over multiple fabs with millions of sensors, analyzing hundreds of petabytes of data. By providing real-time visibility into the manufacturing process, Synopsys enables predictive analytics and optimizes product quality and yield to help give semiconductor fabs a leg up in this competitive landscape.

Synopsys has introduced an AI/ML enabled software offering, Fab.da, to make semiconductor manufacturing efficient. Fab.da is a part of the Synopsys EDA Data Analytics solution, which brings together data analytics and insights from the entire chip lifecycle

It offers a complete data continuum by bringing together these different data types from many different sources into one platform for both advanced and mature node chips. This data continuum allows for high user productivity, maximum data scalability, and increased speed and accuracy in root cause analysis for issues.

Delivering process control solutions to manage complexity at leading-edge fabs, Fab.da can help chip designers and manufacturers drive operational excellence and productivity, providing a competitive edge in today’s manufacturing landscape.

The post Utilizing Artificial Intelligence For Efficient Semiconductor Manufacturing appeared first on Semiconductor Engineering.