The new Particle Tachyon is a 2.7GHz single-board computer (SBC) with 5G connectivity and a whopping 12 TOPS of AI-optimized GPU acceleration.
The post Particle Return to their Roots to Kickstart New AI-Enhanced 5G IoT SBC appeared first on Make: DIY Projects and Ideas for Makers.
The new Particle Tachyon is a 2.7GHz single-board computer (SBC) with 5G connectivity and a whopping 12 TOPS of AI-optimized GPU acceleration.
The post Particle Return to their Roots to Kickstart New AI-Enhanced 5G IoT SBC appeared first on Make: DIY Projects and Ideas for Makers.
The new Particle Tachyon is a 2.7GHz single-board computer (SBC) with 5G connectivity and a whopping 12 TOPS of AI-optimized GPU acceleration.
The post Particle Return to their Roots to Kickstart New AI-Enhanced 5G IoT SBC appeared first on Make: DIY Projects and Ideas for Makers.
From Make: Vol. 87: New evolutions in dev boards make this a metamorphic period for Makers.
The post Boards Guide 2024: Boards Are Back appeared first on Make: DIY Projects and Ideas for Makers.
Particle's new M-series of wireless solutions feature Wi-Fi, cellular, LoRaWAN, and satellite on a single board.
The post Particle’s New M-Series Connects Everything, Everywhere, All At Once appeared first on Make: DIY Projects and Ideas for Makers.
Surely you’ve been there: you need to capture serial output from a microcontroller or other device, so you reach for a PL2303 or CP210x or FT232RL-based USB-to-TTL serial cable (if you can remember where you put the damn thing after you last used it!) and…realize you don’t have the drivers installed on the computer you […]
The post Smarter Serial Communications with WiSer appeared first on Make: DIY Projects and Ideas for Makers.
The first commercial silicon chip that includes open-source, built-in hardware security was announced today by the OpenTitan coalition.
This milestone represents another step in the growth of the open hardware movement. Open hardware has been gaining steam since the development of the popular open-source processor architecture RISC-V.
RISC-V gives an openly available prescription for how a computer can operate efficiently at the most basic level. OpenTitan goes beyond RISC-V’s open-source instruction set by delivering an open-source design for the silicon itself. Although other open-source silicon has been developed, this is the first one to include the design-verification stage and to produce a fully functional commercial chip, the coalition claims.
Utilizing a RISC-V based processor core, the chip, called Earl Grey, includes a number of built-in hardware security and cryptography modules, all working together in a self-contained microprocessor. The project began back in 2019 by a coalition of companies, started by Google and shepherded by the nonprofit lowRISC in Cambridge, United Kingdom. Modeled after open-source software projects, it has been developed by contributors from around the world, both official affiliates with the project and independent coders. Today’s announcement is the culmination of five years of work.
Open source “just takes over because it has certain valuable properties... I think we’re seeing the beginning of this now with silicon.”—Dominic Rizzo, zeroRISC
“This chip is very, very exciting,” says OpenTitan cocreator and CEO of coalition partner zeroRISC Dominic Rizzo. “But there’s a much bigger thing here, which is the development of this whole new type of methodology. Instead of a traditional…command and control style structure, this is distributed.”
The methodology they have developed is called Silicon Commons. Open-source hardware design faces challenges that open-source software didn’t, such as greater costs, a smaller professional community, and inability to supply bug fixes in patches after the product is released, explains lowRISC CEO Gavin Ferris. The Silicon Commons framework provides rules for documentation, predefined interfaces, and quality standards, as well as the governance structure laying out how the different partners make decisions as a collective.
Another key to the success of the project, Ferris says, was picking a problem that all the partners would have an incentive to continue participating in over the course of the five years of development. Hardware security was the right fit for the job because of its commercial importance as well as its particular fit to the open-source model. There’s a notion in cryptography known as Kerckhoffs’s principle, which states that the only thing that should actually be secret in a cryptosystem is the secret key itself. Open-sourcing the entire protocol makes sure the cryptosystem conforms to this rule.
OpenTitan uses a hardware security protocol known as a root of trust (RoT). The idea is to provide an on-chip source of cryptographic keys that is inaccessible remotely. Because it’s otherwise inaccessible, the system can trust that it hasn’t been tampered with, providing a basis to build security on. “Root of Trust means that at the end of the day, there is something that we both believe in,” explains Ravi Subrahmanyan, senior director of integrated circuit design at Analog Devices, who was not involved in the effort. Once there is something both people agree on, a trusted secure connection can be established.
Conventional, proprietary chips can also leverage RoT technology. Open-sourcing it provides an extra layer of trust, proponents argue. Since anyone can inspect and probe the design, the theory is that bugs are more likely to get noticed and the bug fixes can be verified. “The openness is a good thing,” says Subrahmanyan. “Because for example, let’s say a proprietary implementation has some problem. I won’t necessarily know, right? I’m at their mercy as to whether they’re going to tell me or not.”
This kind of on-chip security is especially relevant in devices forming the Internet of Things (IoT), which suffer from unaddressed security challenges. ZeroRISC and its partners will open up sales to IoT markets via an early-access program, and they anticipate broad adoption in that sphere.
Rizzo and Ferris believe their chip has a template for open-source hardware development that other collaborations will replicate. On top of providing transparent security, open-sourcing saves companies money by allowing them to reuse hardware components rather than having to independently develop proprietary versions of the same thing. It also opens the door for many more partners to participate in the effort, including academic institutions such as OpenTitan coalition partner ETH Zurich. Thanks to academic involvement, OpenTitan was able to incorporate cryptography protocols that are safe against future quantum computers.
“Once the methodology has been proven, others will pick it up,” Rizzo says. “If you look at what’s happened with open-source software, first, people thought it was kind of an edge pursuit, and then it ended up running almost every mobile phone. It just takes over because it has certain valuable properties. And so I think we’re seeing the beginning of this now with silicon.”
Surely you’ve been there: you need to capture serial output from a microcontroller or other device, so you reach for a PL2303 or CP210x or FT232RL-based USB-to-TTL serial cable (if you can remember where you put the damn thing after you last used it!) and…realize you don’t have the drivers installed on the computer you […]
The post Smarter Serial Communications with WiSer appeared first on Make: DIY Projects and Ideas for Makers.
A technical paper titled “Low Power and Temperature-Resilient Compute-In-Memory Based on Subthreshold-FeFET” was published by researchers at Zhejiang University, University of Notre Dame, Technical University of Munich, Munich Institute of Robotics and Machine Intelligence, and the Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of Zhejiang Province.
“Compute-in-memory (CiM) is a promising solution for addressing the challenges of artificial intelligence (AI) and the Internet of Things (IoT) hardware such as ‘memory wall’ issue. Specifically, CiM employing nonvolatile memory (NVM) devices in a crossbar structure can efficiently accelerate multiply-accumulation (MAC) computation, a crucial operator in neural networks among various AI models. Low power CiM designs are thus highly desired for further energy efficiency optimization on AI models. Ferroelectric FET (FeFET), an emerging device, is attractive for building ultra-low power CiM array due to CMOS compatibility, high ION /IOF ratio, etc. Recent studies have explored FeFET based CiM designs that achieve low power consumption. Nevertheless, subthreshold-operated FeFETs, where the operating voltages are scaled down to the subthreshold region to reduce array power consumption, are particularly vulnerable to temperature drift, leading to accuracy degradation. To address this challenge, we propose a temperature-resilient 2T-1FeFET CiM design that performs MAC operations reliably at subthreahold region from 0 to 85 Celsius, while consuming ultra-low power. Benchmarked against the VGG neural network architecture running the CIFAR-10 dataset, the proposed 2T-1FeFET CiM design achieves 89.45% CIFAR-10 test accuracy. Compared to previous FeFET based CiM designs, it exhibits immunity to temperature drift at an 8-bit wordlength scale, and achieves better energy efficiency with 2866 TOPS/W.”
Find the technical paper here. Published January 2024 (preprint).
Zhou, Yifei, Xuchu Huang, Jianyi Yang, Kai Ni, Hussam Amrouch, Cheng Zhuo, and Xunxhao Yin. “Low Power and Temperature-Resilient Compute-In-Memory Based on Subthreshold-FeFET.” arXiv preprint arXiv:2312.17442 (2023).
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The post Ultra-Low Power CiM Design For Practical Edge Scenarios appeared first on Semiconductor Engineering.
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