Cadence’s Reela Samuel explores the critical role of PCIe 6.0 equalization in maintaining signal integrity and solutions to mitigate verification challenges, such as creating checkers to verify all symbols of TS0, ensuring the correct functioning of scrambling, and monitoring phase and LTSSM state transitions.

Siemens’ John McMillan introduces an advanced packaging flow for Intel’s Embedded Multi-die Interconnect Bridge (EMIB) technology, including technical challenges, design methodologies, and the integration of EMIBs in system-level package designs.

Synopsys’ Dustin Todd checks out what’s next for the U.S. CHIPS and Science Act, including the establishment of the National Semiconductor Technology Center and the allocation of $13 billion for research and development efforts.

Keysight’s Roberto Piacentini Filho explores the challenges of managing the large design files and massive volumes of data involved in a modern chip design project, which can take up as much as a terabyte of disk space and involve hundreds of thousands of files.

Arm’s Sandeep Mistry shows how ML models developed for mobile computer vision applications and requiring tens to hundreds of millions of multiply-accumulate (MACs) operations per inference can be deployed to a modern microcontroller.

Ansys’ Aliyah Mallak explores an effort to manufacture biotech products in microgravity and how simulation helps ensure payloads containing delicate, temperature-sensitive spore samples and bioreactors make it safely to the International Space Station or low Earth orbit safely.

Micron Technology’s Amit Srivastava, ULVAC’s Brian Coppa, and SEMI’s Mark da Silva suggest tackling corporate sustainability goals with a bottom-up approach that leverages various sensing technologies, at the cleanroom, sub-fab, and facilities levels for both greenfield and brownfield device-making facilities, to enable predictive analytics.

And don’t miss the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

Amkor’s JeongMin Ju shows how to prevent critical failures in copper RDLs caused by overcurrent-induced fusing.

Synopsys’ Al Blais discusses curvilinear checking and fracture requirements for the MULTIGON era.

Lam Research’s Dempsey Deng compares the parasitic capacitance of a 6F² honeycomb DRAM device to a 4F² VCAT DRAM structure.

Brewer Science’s Jessica Albright covers debonding methods, thermal, topography, adhesion, and thickness variation.

SEMI’s John Cooney reviews a fireside chat between the President of SEMI Americas and the U.S. Under Secretary of State for Economic Growth, Energy, and the Environment on securing supply chains.

The post Blog Review: Aug. 21 appeared first on Semiconductor Engineering.

EUV mirror interference lithography

Researchers from the Paul Scherrer Institute developed an EUV lithography technique that can produce conductive tracks with a separation of just five nanometers by exposing the sample indirectly rather than directly.

Called EUV mirror interference lithography (MIL), the technique uses two mutually coherent beams that are reflected onto the wafer by two identical mirrors. The beams then create an interference pattern whose period depends on both the angle of incidence and the wavelength of the light. In addition to the 5nm resolution, the conductive tracks were found to have high contrast and sharp edges.

“Our results show that EUV lithography can produce extremely high resolutions, indicating that there are no fundamental limitations yet. This is really exciting since it extends the horizon of what we deem as possible and can also open up new avenues for research in the field of EUV lithography and photoresist materials,” said Dimitrios Kazazis of the Laboratory of X-ray Nanoscience and Technologies at PSI in a statement.

The method is currently too slow for industrial chip production and can produce only simple and periodic structures. However, the team sees it as a resource for early development of new photoresists and plans to continue research to improve its performance and capabilities. [1]

Artificial sapphire dielectrics

Researchers from Shanghai Institute of Microsystem and Information Technology created artificial sapphire dielectric wafers made of single-crystalline aluminum oxide (Al₂O₃).

“The aluminum oxide we created is essentially artificial sapphire, identical to natural sapphire in terms of crystal structure, dielectric properties and insulation characteristics,” said Tian Zi’ao, a researcher at SIMIT, in a release.

“By using intercalation oxidation technology on single-crystal aluminum, we were able to produce this single-crystal aluminum oxide dielectric material,” added Di Zengfeng, a researcher at SIMIT, in a release. “Unlike traditional amorphous dielectric materials, our crystalline sapphire can achieve exceptionally low leakage at just one-nanometer level.”

The researchers hope the improved dielectric properties could lead to more power-efficient devices. [2]

Accelerating computation on sparse data sets

Researchers from Lehigh University and Lawrence Berkeley National Laboratory developed specialized hardware that enables faster computation on data sets that have a high number of zero values, frequent in the fields of bioinformatics and physical sciences. The hardware is portable and can be integrated into general-purpose multi-core computers.

“The accelerating sparse accumulation (ASA) architecture includes a hardware buffer, a hardware cache, and a hardware adder. It takes two sparse matrices, performs a matrix multiplication, and outputs a sparse matrix. The ASA only uses non-zero data when it performs this operation, which makes the architecture more efficient. The hardware buffer and the cache allow the computer processor to easily manage the flow of data; the hardware adder allows the processor to quickly generate values to fill up the empty matrices,” explained Berkely Lab’s Ingrid Ockert in a press release. “Once these values are calculated, the ASA system produces an output. This operation is a building block that the researcher can then use in other functions. For instance, researchers could use these outputs to generate graphs or they could process these outputs through other algorithms such as a Sparse General Matrix-Matrix Multiplication (SpGEMM) algorithm.”

The ASA architecture could accelerate a variety of algorithms. Microbiome research is presented as an example, where it could be used to run metagenomic assembly and similarity clustering algorithms such as Markov Cluster Algorithms that quickly characterize the genetic markers of all of the organisms in a soil sample. [3]

References

[1] I. Giannopoulos, I. Mochi, M. Vockenhuber, Y. Ekinci & D. Kazazis. Extreme ultraviolet lithography reaches 5 nm resolution. Nanoscale, 12.08.2024 https://doi.org/10.1039/D4NR01332H

[2] Zeng, D., Zhang, Z., Xue, Z. et al. Single-crystalline metal-oxide dielectrics for top-gate 2D transistors. Nature (2024). https://doi.org/10.1038/s41586-024-07786-2

[3] Chao Zhang, Maximilian Bremer, Cy Chan, John M Shalf, and Xiaochen Guo. ASA: Accelerating Sparse Accumulation in Column-wise SpGEMM. ACM Transactions on Architecture and Code Optimization (TACO) Volume 19, Issue 4, Article No.: 49, Pages 1-24 https://doi.org/10.1145/3543068

The post Research Bits: Aug. 20 appeared first on Semiconductor Engineering.

Measuring temperature with neutrons

Researchers from Osaka University, National Institutes for Quantum Science and Technology, Hokkaido University, Japan Atomic Energy Agency, and Tokamak Energy developed a way to rapidly measure the temperature of electronic components inside a device using neutrons.

The technique, called ‘neutron resonance absorption’ (NRA), examines neutrons being absorbed by atomic nuclei at certain energy levels to determine the properties of the material. After being generated using high-intensity laser beans, the neutrons were then decelerated to a very low energy level before being passed through the sample, in this case plates of tantalum and silver. The temporal signal of the NRA was altered in a predictable manner when the sample material’s temperature was changed.

“This technology makes it possible to instantaneously and accurately measure temperature,” said Zechen Lan of Osaka University, in a statement. “As our method is non-destructive, it can be used to monitor devices like batteries and semiconductor devices.”

The technique can acquire temperature data in a window of 100 nanoseconds, and the measurement device itself is about a tenth of the size of similar equipment.

“Using lasers to generate and accelerate ions and neutrons is nothing new, but the techniques we’ve developed in this study represent an exciting advance,” added Akifumi Yogo of Osaka University, in a statement. “We expect that the high temporal resolution will allow electronics to be examined in greater detail, help us to understand normal operating conditions, and pinpoint abnormalities.” [1]

Mapping heat transfer

Researchers from the University of Rochester applied optical super-resolution fluorescence microscopy techniques used in biological imaging to map heat transfer in electronic devices using luminescent nanoparticles.

By applying highly doped upconverting nanoparticles to the surface of a device, the researchers were able to achieve super-high resolution thermometry at the nanoscale level from up to 10 millimeters away.

Rochester researchers demonstrated their super-high resolution thermometry techniques on an electrical heater structure that the team designed to produce sharp temperature gradients. (Credit: University of Rochester / J. Adam Fenster)

“The building blocks of our modern electronics are transistors with nanoscale features, so to understand which parts of overheating, the first step is to get a detailed temperature map,” said Andrea Pickel, an assistant professor from the University of Rochester’s Department of Mechanical Engineering, in a release. “But you need something with nanoscale resolution to do that.”

The researchers demonstrated the technique using an electrical heater structure designed to produce sharp temperature gradients. To improve the process, the team hopes to lower the laser power used and refine the methods for applying layers of nanoparticles to the devices. [2]

ML for predicting thermal properties

Researchers from MIT, Argonne National Laboratory, Harvard University, the University of South Carolina, Emory University, the University of California at Santa Barbara, and Oak Ridge National Laboratory propose a new machine learning framework that provides much faster prediction of phonon dispersion relations, an important measurement for determining the thermal properties of a material and how heat moves through semiconductors and insulators.

Heat-carrying phonons have an extremely wide frequency range, and the particles interact and travel at different speeds. “Phonons are the culprit for the thermal loss, yet obtaining their properties is notoriously challenging, either computationally or experimentally,” said Mingda Li, associate professor of nuclear science and engineering at MIT, in a release.

The researchers started with a graph neural network (GNN) that converts a material’s atomic structure into a crystal graph comprising multiple nodes, which represent atoms, connected by edges, which represent the interatomic bonding between atoms.

To make it suitable for predicting phonon dispersion relations, they created a virtual node graph neural network (VGNN) by adding a series of flexible virtual nodes to the fixed crystal structure to represent phonons. This enabled the VGNN to skip many complex calculations when estimating phonon dispersion relations, making it a more efficient method than a standard GNN.

Li noted that a VGNN could be used to calculate phonon dispersion relations for a few thousand materials in a few seconds with a personal computer. The technique could also be used to predict challenging optical and magnetic properties. [3]

References

[1] Lan, Z., Arikawa, Y., Mirfayzi, S.R. et al. Single-shot laser-driven neutron resonance spectroscopy for temperature profiling. Nat Commun 15, 5365 (2024). https://doi.org/10.1038/s41467-024-49142-y

[2] Ziyang Ye et al., Optical super-resolution nanothermometry via stimulated emission depletion imaging of upconverting nanoparticles. Sci. Adv. 10, eado6268 (2024) https://doi.org/10.1126/sciadv.ado6268

[3] Okabe, R., Chotrattanapituk, A., Boonkird, A. et al. Virtual node graph neural network for full phonon prediction. Nat Comput Sci 4, 522–531 (2024). https://doi.org/10.1038/s43588-024-00661-0

The post Research Bits: Aug. 5 appeared first on Semiconductor Engineering.

On-chip microcapacitors

Scientists from Lawrence Berkeley National Laboratory and University of California Berkeley developed microcapacitors with ultrahigh energy and power density that could be used for on-chip energy storage.

The microcapacitors were made with thin films of hafnium oxide (HfO₂) and zirconium oxide (ZrO₂) engineered to achieve a negative capacitance effect, which increased overall capacitance and enabled it to store greater amounts of charge.

“We’ve shown that it’s possible to store a lot of energy in microcapacitors made from engineered thin films, much more than what is possible with ordinary dielectrics,” said Sayeef Salahuddin, a Berkeley Lab faculty senior scientist and UC Berkeley professor, in a release. “What’s more, we’re doing this with a material that can be processed directly on top of microprocessors.”

The films were grown with atomic layer deposition. The ratio of HfO₂ and ZrO₂ leads the films to be either ferroelectric or antiferroelectric. Balancing the composition at the tipping point between the two gives rise to the negative capacitance effect where the material can be very easily polarized by even a small electric field.

By interspersing atomically thin layers of aluminum oxide after every few layers of HfO₂-ZrO₂, they could grow the films up to 100 nm thick and integrate them into 3D trench capacitor structures. The researchers claim the microcapacitor shows 9x higher energy density and 170x higher power density compared to today’s electrostatic capacitors. They are working on scaling up the technology and integrating it into full-size microchips. [1]

Deformable micro-supercapacitor

Researchers from Pohang University of Science and Technology (POSTECH) and Korea Institute of Industrial Technology (KITECH) built a micro-supercapacitor (MSC) capable of stretching, twisting, folding, and wrinkling.

The team used laser ablation for fine patterning of both eutectic gallium-indium liquid metal (EGaIn) and graphene layers on a stretchable polystyrene-block-poly(ethylene-co-butylene)-block-polystyrene copolymer (SEBS) substrate.

The MSC retailed its areal capacitance after stretching up to 1,000 cycles and operated stably while being mechanically deformed. [2]

Oriented 2D nanofillers

Researchers from the University of Houston, Jackson State University, and Howard University have developed a flexible high-energy-density capacitor created using layered polymers with mechanically exfoliated flakes of 2D materials as nanofillers.

By arranging materials like mica and hexagonal boron nitride (hBN) in specific layers, they created a thin sandwich-like structure with higher energy density and efficiency than capacitors with randomly blended-in nanofillers.

“Our work demonstrates the development of high energy and high-power density capacitors by blocking electrical breakdown pathways in polymeric materials using the oriented 2D nanofillers,” said Maninderjeet Singh, a University of Houston chemical engineering PhD graduate and now a postdoctoral research scientist at Columbia University, in a release. “We achieved an ultra-high energy density of approximately 75 J/cm³, the highest reported for a polymeric dielectric capacitor to date.” [3]

References

[1] Cheema, S.S., Shanker, N., Hsu, SL. et al. Giant energy storage and power density negative capacitance superlattices. Nature (2024). https://doi.org/10.1038/s41586-024-07365-5

[2] Kim, KW., Park, S.J., Park, SJ. et al. Deformable micro-supercapacitor fabricated via laser ablation patterning of Graphene/liquid metal. npj Flex Electron 8, 18 (2024). https://doi.org/10.1038/s41528-024-00306-2

[3] Singh, M., Das, P., Samanta, P. N., et al. Ultrahigh Capacitive Energy Density in Stratified 2D Nanofiller-Based Polymer Dielectric Films. ACS Nano 2023 17 (20), 20262-20272. https://doi.org/10.1021/acsnano.3c06249

The post Research Bits: May 13 appeared first on Semiconductor Engineering.

Cadence’s Vatsal Patel stresses the importance of having testing and training capabilities for high-bandwidth memory to prevent the entire SoC from becoming useless and points to key HBM DRAM test instructions through IEEE 1500.

In a podcast, Siemens’ Stephen V. Chavez chats with Anaya Vardya of American Standard Circuits about the growing significance of high density interconnect and Ultra HDI technologies, which enable denser component placement and increased signal integrity compared to traditional PCB designs.

Synopsys’ Ian Land and Randy Fish find that silicon lifecycle management is increasingly being used on chips that target the aerospace and government market to ensure system health and longevity.

Arm’s Hristo Belchev looks at how to enable testing of system designs using the Memory Partitioning and Monitoring (MPAM) Arm architecture supplement, which allows privileged software to partition caches, memory controllers and interconnects on the hardware level.

Keysight’s Jonathon Wright considers where generative AI can add value in software testing by proposing a wide range of scenarios and improving communication between different stakeholders.

Ansys’ Laura Carter checks out how simulation is used to reduce the risks to drivers during a crash in stock car racing.

SEMI’s Maria Daniela Perez chats with Owen J. Guy of Swansea University about the challenge of onboarding talent within the microelectronics industry and the importance of ensuring students receive hands-on experience and exposure to real-world applications.

And don’t miss the blogs featured in the latest Systems & Design newsletter:

Technology Editor Brian Bailey suggests that although it is great to see the DAC conference come back to life, EDA companies need to do something about the show floor.

Siemens’ John Ferguson shows how to glean useful information well before all the details of an assembly are known.

Axiomise’ Ashish Darbari explains how formal verification can help improve chips.

Arteris’ Frank Schirrmeister tracks the race to centralized computing in automotive.

Synopsys’ Andrew Appleby explores the co-optimization of foundation IP and design flows for new transistors.

Cadence’s Anika Sunda looks at controlling the access to physical memory addresses.

Keysight’s Ben Coffin digs into how AI will be used in just about every subsystem of 6G networks.

The post Blog Review: May 1 appeared first on Semiconductor Engineering.

Siemens’ John McMillan digs into physical verification maturity for high-density advanced packaging (HDAP) designs and major differences in the LVS verification flow compared to the well-established process for SoCs.

Synopsys’ Varun Shah identifies why a cloud adoption framework is key to getting the most out of deploying EDA tools in the cloud, including by ensuring that different types of necessary compute are accessible for all stages of the design cycle.

Cadence’s Reela Samuel suggests that a chiplet-based approach will provide improved performance and reduced complexity for the automotive sector, enabling OEMs to construct a robust yet flexible electronic architecture.

Keysight’s Emily Yan finds that today’s chip design landscape is facing challenges reminiscent of those encountered by the Large Hadron Collider in managing data volume, version control, and global collaboration.

Ansys’ Raha Vafaei explains why the finite-difference time-domain (FDTD) method, an algorithmic approach to solving Maxwell’s equations, is key for modeling nanophotonic devices, processes, and materials.

Arm’s Ed Player explains the different components of the Common Microcontroller Software Interface Standard (CMSIS) to help identify which are useful for particular Arm-based microcontroller projects.

SEMI’s Mark da Silva, Nishita Rao and Karim Somani check out the state of digital twins in semiconductor manufacturing and challenges such as the need for standardization and communication between different digital twins.

Plus, check out the blogs featured in the latest Low Power-High Performance newsletter:

Rambus’ Lou Ternullo looks at why performance demands of generative AI and other advanced workloads will require new architectural solutions enabled by CXL.

Ansys’ Raha Vafaei shines a light on how the evolution of photonics engineering will encompass novel materials and cutting-edge techniques.

Siemens’ Keith Felton explains why embracing emerging approaches is essential for crafting IC packages that address the evolving demands of sustainability, technology, and consumer preferences.

Cadence’s Mark Seymour lays out how CFD simulation software can predict time-dependent aspects and various failure scenarios for data center managers.

Arm’s Adnan Al-Sinan and Gian Marco Iodice point out that LLMs already run well on small devices, and that will only improve as models become smaller and more sophisticated.

Keysight’s Roberto Piacentini Filho shows how a modular approach can improve yield, reduce cost, and improve PPA/C.

Quadric’s Steve Roddy finds that smart local memory in an AI/ML subsystem solves SoC bottlenecks.

Synopsys’ Ian Land, Kenneth Larsen, and Rob Aitken detail why the traditional approach using monolithic system-on-chips (SoCs) falls short when addressing the complex needs of modern systems.

The post Blog Review: Feb. 21 appeared first on Semiconductor Engineering.

DNA assembly of 3D nanomaterials

Scientists from Brookhaven National Laboratory, Columbia University, and Stony Brook University developed a method that uses DNA to instruct molecules to organize themselves into targeted 3D patterns and produce a wide variety of designed metallic and semiconductor 3D nanostructures.

“We have been using DNA to program nanoscale materials for more than a decade,” said corresponding author Oleg Gang, a professor of chemical engineering and of applied physics and materials science at Columbia Engineering, in a release. “Now, by building on previous achievements, we have developed a method for converting these DNA-based structures into many types of functional inorganic 3D nano-architectures, and this opens tremendous opportunities for 3D nanoscale manufacturing.”

Researchers program strands of DNA to “direct” the self-assembly process towards molecular arrangements that give rise to properties such as electrical conductivity, photosensitivity, and magnetism, which can then be scaled up to functional materials.

The team used the method to grow silica on a DNA lattice, which helped to create a robust structure. They then used vapor-phase infiltration and liquid-phase infiltration, which bonds a precursor chemical in vapor or liquid form to a nanoscale lattice, to produce a variety of 3D metallic structures.

Scientists used a new, universal method to create a variety of 3D metallic and semiconductor nanostructures, including this structure revealed by an electron microscope. The scale bar represents one micrometer. The superimposed graphics convey that the researchers combined multiple techniques to layer silicon dioxide, then alumina-doped zinc oxide, and finally platinum on top of a DNA “scaffolding.” This complex structure represents new possibilities for advanced manufacturing at small scales. (Credit: Brookhaven National Laboratory)

“Stacking these techniques showed much more depth of control than has ever been accomplished before,” said Aaron Michelson, a postdoctoral researcher at Brookhaven’s Center for Functional Nanomaterials, in a release. “Whatever vapors are available as precursors for vapor-phase infiltration can be coupled with various metal salts compatible with liquid-phase infiltration to create more complex structures. For example, we were able to combine platinum, aluminum, and zinc on top of one nanostructure.”

They were also able to add on semiconducting metal oxides, such as zinc oxide, to an insulating nanostructure, providing it with electrical conductivity and photoluminescent properties. [1]

Mott insulator transistor

Researchers from the University of Nebraska-Lincoln, Brookhaven National Laboratory, University of the Basque Country, and NYU Shanghai propose a way to make transistors out of Mott insulators.

The researchers were able to direct the Mott transition from insulator to metal and back again by topping a Mott insulator with a gate insulator made of a ferroelectric material and using a voltage to flip the ferroelectric material’s polarization. A third layer beneath the Mott channel that allows charges to migrate from the Mott down to it improved control over the insulator-metal transition with an on-off ratio of 385.

Additionally, the researchers claim that the Mott-ferroelectric pairing is more energy-efficient than other non-volatile but magnetism-based memory, including MRAM.

“We can have very high-performance devices, retaining many manufacturing processes of conventional semiconductors and overcoming some fundamental limitations of them,” said Xia Hong, professor of physics at the University of Nebraska-Lincoln, in a release. “I think it’s ready. It’s really competitive with other non-volatile memory technologies.” [2]

Faster wireless data speeds

Researchers from Osaka University and IMRA America suggest a way to increase wireless data transmission speeds by reducing the noise in the system using lasers.

Future 6G transmitters and receivers are expected to use the sub-terahertz band, which extends from 100 GHz to 300 GHz, using an approach called “multi-level signal modulation” to further increase the data transmission rate. However, this approach is highly sensitive to noise at the upper end of the frequency range.

“This problem has limited 300-GHz communications so far,” said Keisuke Maekawa of Osaka University in a statement. “However, we found that at high frequencies, a signal generator based on a photonic device had much less phase noise than a conventional electrical signal generator.”

The team used a stimulated Brillouin scattering laser, which employs interactions between sound and light waves, to generate a precise signal. They then set up a 300 GHz-band wireless communication system that employs the laser-based signal generator in both the transmitter and receiver. The system also used on-line digital signal processing (DSP) to demodulate the signals in the receiver and increase the data rate.

“Our team achieved a single-channel transmission rate of 240 gigabits per second,” said Tadao Nagatsuma, a professor at Osaka University, in a release. “This is the highest transmission rate obtained so far in the world using on-line DSP.” The researchers expect that with multiplexing techniques and more sensitive receivers, the data rate can be increased to 1 terabit per second. [3]

References

[1] Aaron Michelson et al., Three-dimensional nanoscale metal, metal oxide, and semiconductor frameworks through DNA-programmable assembly and templating. Sci. Adv. 10, eadl0604 (2024). https://doi.org/10.1126/sciadv.adl0604

[2] Hao, Y., Chen, X., Zhang, L. et al. Record high room temperature resistance switching in ferroelectric-gated Mott transistors unlocked by interfacial charge engineering. Nat Commun 14, 8247 (2023). https://doi.org/10.1038/s41467-023-44036-x

[3] Keisuke Maekawa, Tomoya Nakashita, Toki Yoshioka, Takashi Hori, Antoine Rolland, Tadao Nagatsuma, Single-channel 240-Gbit/s sub-THz wireless communications using ultra-low phase noise receiver, IEICE Electronics Express, Article ID 20.20230584, Advance online publication December 25, 2023, Online ISSN 1349-2543, https://doi.org/10.1587/elex.20.20230584

The post Research Bits: Feb. 19 appeared first on Semiconductor Engineering.