Cadence’s Reela Samuel explores the critical role of PCIe 6.0 equalization in maintaining signal integrity and solutions to mitigate verification challenges, such as creating checkers to verify all symbols of TS0, ensuring the correct functioning of scrambling, and monitoring phase and LTSSM state transitions.

Siemens’ John McMillan introduces an advanced packaging flow for Intel’s Embedded Multi-die Interconnect Bridge (EMIB) technology, including technical challenges, design methodologies, and the integration of EMIBs in system-level package designs.

Synopsys’ Dustin Todd checks out what’s next for the U.S. CHIPS and Science Act, including the establishment of the National Semiconductor Technology Center and the allocation of $13 billion for research and development efforts.

Keysight’s Roberto Piacentini Filho explores the challenges of managing the large design files and massive volumes of data involved in a modern chip design project, which can take up as much as a terabyte of disk space and involve hundreds of thousands of files.

Arm’s Sandeep Mistry shows how ML models developed for mobile computer vision applications and requiring tens to hundreds of millions of multiply-accumulate (MACs) operations per inference can be deployed to a modern microcontroller.

Ansys’ Aliyah Mallak explores an effort to manufacture biotech products in microgravity and how simulation helps ensure payloads containing delicate, temperature-sensitive spore samples and bioreactors make it safely to the International Space Station or low Earth orbit safely.

Micron Technology’s Amit Srivastava, ULVAC’s Brian Coppa, and SEMI’s Mark da Silva suggest tackling corporate sustainability goals with a bottom-up approach that leverages various sensing technologies, at the cleanroom, sub-fab, and facilities levels for both greenfield and brownfield device-making facilities, to enable predictive analytics.

And don’t miss the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

Amkor’s JeongMin Ju shows how to prevent critical failures in copper RDLs caused by overcurrent-induced fusing.

Synopsys’ Al Blais discusses curvilinear checking and fracture requirements for the MULTIGON era.

Lam Research’s Dempsey Deng compares the parasitic capacitance of a 6F² honeycomb DRAM device to a 4F² VCAT DRAM structure.

Brewer Science’s Jessica Albright covers debonding methods, thermal, topography, adhesion, and thickness variation.

SEMI’s John Cooney reviews a fireside chat between the President of SEMI Americas and the U.S. Under Secretary of State for Economic Growth, Energy, and the Environment on securing supply chains.

The post Blog Review: Aug. 21 appeared first on Semiconductor Engineering.

Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML.

Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government disagreements over how to fund chip R&D, according to Bloomberg.

SEMI published a position paper this week cautioning the European Union against imposing additional export controls to allow companies, encouraging them to  be “as free as possible in their investment decisions to avoid losing their agility and relevance across global markets.” SEMI’s recommendations on outbound investments are in response to the European Economic Security Strategy and emphasize the need for a transparent and predictable regulatory framework.

The U.S. may restrict China’s access to HBM chips and the equipment needed to make them, reports Bloomberg. Today those chips are manufactured by two Korean-based companies, Samsung and SK hynix, but U.S.-based Micron expects to begin shipping 12-high stacks of HBM3E in 2025, and is currently working on HBM4.

Synopsys executive chair and founder Dr. Aart de Geus was named the winner of the Semiconductor Industry Association’s Robert N. Noyce Award. De Geus was selected due to his contributions to EDA technology over a career spanning more than four decades.

The top three foundries plan to implement high-NA EUV lithography as early as 2025 for the 18 angstrom generation, but the replacement of single exposure high-NA (0.55) over double patterning with standard EUV (NA = 0.33) depends on whether it provides better results at a reasonable cost per wafer.

Quick links to more news:

Global
In-Depth
Market Reports and Earnings
Education and Training
Security
Product News
Research
Events and Further Reading

Global

Belgium-based Imec released part 2 of its chiplets series, addressing testing strategies and standardization efforts, as well as guidelines and research “towards efficient ESD protection strategies for advanced 3D systems-on-chip.”

Also in Belgium, BelGan, maker of GaN chips, filed for bankruptcy according to the Brussels Times.

TSMC‘s Dresden, Germany, plant will break ground this month.

The UK will dole out more than £100 million (~US $128 million) in funding to develop five new quantum research hubs in Glasgow, Edinburgh, Birmingham, Oxford, and London.

MassPhoton is opening Hong Kong‘s first ultra-high vacuum GaN epitaxial wafer pilot line and will establish a GaN research center.

Infineon completed the sale of its manufacturing sites in the Philippines and South Korea to ASE.

Israel-based RAAAM Memory Technologies received a €5.25 million grant from the European Innovation Council (EIC) to support the development and commercialization of its innovative memory solutions. This funding will enable RAAAM to advance its research in high-performance and energy-efficient memory technologies, accelerating their integration into various applications and markets.

In-Depth

Semiconductor Engineering published its Automotive, Security and Pervasive Computing newsletter this week, featuring these top stories and video:

• Chip Security Now Depends On Widening Supply Chain
• Defining Chip Threat Models To Determining Security Risks
• Post-Quantum Computing Threatens Fundamental Transport Protocols

And:

• Where Power Savings Really Count
• Making Electronics More Efficient (video)

Market Reports and Earnings

The semiconductor equipment industry is on a positive trajectory in 2024, with moderate revenue growth observed in Q2 after a subdued Q1, according to a new report from Yole Group. Wafer Fab Equipment revenue is projected to grow by 1.3% year-on-year, despite a 12% drop in Q1. Test equipment lead times are normalizing, improving order conditions. Key areas driving growth include memory and logic capital expenditures and high-bandwidth memory demand.

Worldwide silicon wafer shipments increased by 7% in Q2 2024, according to SEMI‘s latest report. This growth is attributed to robust demand from multiple semiconductor sectors, driven by advancements in AI, 5G, and automotive technologies.

The RF GaN market is projected to grow to US $2 billion by 2029, a 10% CAGR, according to Yole Group.

Counterpoint released their Q2 smartphone top 10 report.

Renesas completed their acquisition of EDA firm Altium, best known for its EDA platform and freeware CircuitMaker package.

It’s earnings season and here are recently released financials in the chip industry:

AMD  Advantest   Amkor   Ansys  Arteris   Arm   ASE   ASM   ASML
Cadence  IBM   Intel   Lam Research   Lattice   Nordson   NXP   Onsemi 
Qualcomm   Rambus  Samsung    SK Hynix   STMicro   Teradyne    TI  
Tower  TSMC    UMC  Western Digital

Industry stock price impacts are here.

Education and Training

Rochester Institute of Technology is leading a new pilot program to prepare community college students in areas such as cleanroom operations, new materials, simulation, and testing processes, with the intent of eventual transfer into RIT’s microelectronic engineering program.

Purdue University inked a deal with three research institutions — University of Piraeus, Technical University of Crete, and King’s College London —to develop joint research programs for semiconductors, AI and other critical technology fields.

The European Chips Skills Academy formed the Educational Leaders Board to help bridge the talent gap in Europe’s microelectronics sector.  The Board includes representatives from universities, vocational training providers, educators and research institutions who collaborate on strategic initiatives to strengthen university networks and build academic expertise through ECSA training programs.

Security

The Cybersecurity and Infrastructure Security Agency (CISA) is encouraging Apple users to review and apply this week’s recent security updates.

Microsoft Azure experienced a nearly 10 hour DDoS attack this week, leading to global service disruption for many customers.  “While the initial trigger event was a Distributed Denial-of-Service (DDoS) attack, which activated our DDoS protection mechanisms, initial investigations suggest that an error in the implementation of our defenses amplified the impact of the attack rather than mitigating it,” stated Microsoft in a release.

NIST published:

• “Recommendations For Increasing U.S. Participation and Leadership in Standards Development,” a report outlining cybersecurity recommendations and mitigation strategies.
• Final guidance documents and software to help improve the “safety, security and trustworthiness of AI systems.”
• Cloud Computing Forensic Reference Architecture guide.

Delta Air Lines plans to seek damages after losing $500 million in lost revenue due to security company CrowdStrike‘s software update debacle.  And shareholders are also angry.

Recent security research:

• Physically Secure Logic Locking With Nanomagnet Logic (UT Dallas)
• WBP: Training-time Backdoor Attacks through HW-based Weight Bit Poisoning (UCF)
• S-Tune: SOT-MTJ Manufacturing Parameters Tuning for Secure Next Generation of Computing ( U. of Arizona, UCF)
• Diffie Hellman Picture Show: Key Exchange Stories from Commercial VoWiFi Deployments (CISPA, SBA Research, U. of Vienna)

Product News

Lam Research introduced a new version of its cryogenic etch technology designed to enhance the manufacturing of 3D NAND for AI applications. This technology allows for the precise etching of high aspect ratio features, crucial for creating 1,000-layer 3D NAND.

Fig.1: 3D NAND etch. Source: Lam Research

Alphawave Semi launched its Universal Chiplet Interconnect Express Die-to-Die IP. The subsystem offers 8 Tbps/mm bandwidth density and supports operation at 24 Gbps for D2D connectivity.

Infineon introduced a new MCU series for industrial and consumer motor controls, as well as power conversion system applications. The company also unveiled its new GoolGaN Drive product family of integrated single switches and half-bridges with integrated drivers.

Rambus released its DDR5 Client Clock Driver for next-gen, high-performance desktops and notebooks. The chips include Gen1 to Gen4 RCDs, power management ICs, Serial Presence Detect Hubs, and temperature sensors for leading-edge servers.

SK hynix introduced its new GDDR7 graphics DRAM. The product has an operating speed of 32Gbps, can process 1.5TB of data per second and has a 50% power efficiency improvement compared to the previous generation.

Intel launched its new Lunar Lake Ultra processors. The long awaited chips will be included in more than 80 laptop designs and has more than 40 NPU tera operations per second as well as over 60 GPU TOPS delivering more than 100 platform TOPS.

Brewer Science achieved recertification as a Certified B Corporation, reaffirming its commitment to sustainable and ethical business practices.

Panasonic adopted Siemens’ Teamcenter X cloud product lifecycle management solution, citing Teamcenter X’s Mendix low-code platform, improved operational efficiency and flexibility for its choice.

Keysight validated its 5G NR FR1 1024-QAM demodulation test cases for the first time. The 5G NR radio access technology supports eMBB and was validated on the 3GPP TS 38.521-4 test specification.

Research

In a 47-page deep-dive report, the Center for Security and Emerging Technology delved into all of the scientific breakthroughs from 1980 to present that brought EUV lithography to commercialization, including lessons learned for the next emerging technologies.

Researchers at the Paul Scherrer Institute developed a high-performance X-ray tomography technique using burst ptychography, achieving a resolution of 4nm. This method allows for non-destructive imaging of integrated circuits, providing detailed views of nanostructures in materials like silicon and metals.

MIT signed a four-year agreement with the Novo Nordisk Foundation Quantum Computing Programme at University of Copenhagen, focused on accelerating quantum computing hardware research.

MIT’s Research Laboratory of Electronics (RLE) developed a mechanically flexible wafer-scale integrated photonics fabrication platform. This enables the creation of flexible photonic circuits that maintain high performance while being bendable and stretchable. It offers significant potential for integrating photonic circuits into various flexible substrate applications in wearable technology, medical devices, and flexible electronics.

The Naval Research Lab identified a new class of semiconductor nanocrystals with bright ground-state excitons, emphasizing an important advancement in optoelectronics.

Researchers from National University of Singapore developed a novel method, known as tension-driven CHARM3D,  to fabricate 3D self-healing circuits, enabling the 3D printing of free-standing metallic structures without the need for support materials and external pressure.

Find more research in our Technical Papers library.

Events and Further Reading

Find upcoming chip industry events here, including:

Upcoming webinars are here, including topics such as quantum safe cryptography, analytics for high-volume manufacturing, and mastering EMC simulations for electronic design.

Find Semiconductor Engineering’s latest newsletters here:

Automotive, Security and Pervasive Computing
Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials

The post Chip Industry Week in Review appeared first on Semiconductor Engineering.

Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML.

Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government disagreements over how to fund chip R&D, according to Bloomberg.

SEMI published a position paper this week cautioning the European Union against imposing additional export controls to allow companies, encouraging them to  be “as free as possible in their investment decisions to avoid losing their agility and relevance across global markets.” SEMI’s recommendations on outbound investments are in response to the European Economic Security Strategy and emphasize the need for a transparent and predictable regulatory framework.

The U.S. may restrict China’s access to HBM chips and the equipment needed to make them, reports Bloomberg. Today those chips are manufactured by two Korean-based companies, Samsung and SK hynix, but U.S.-based Micron expects to begin shipping 12-high stacks of HBM3E in 2025, and is currently working on HBM4.

Synopsys executive chair and founder Dr. Aart de Geus was named the winner of the Semiconductor Industry Association’s Robert N. Noyce Award. De Geus was selected due to his contributions to EDA technology over a career spanning more than four decades.

The top three foundries plan to implement high-NA EUV lithography as early as 2025 for the 18 angstrom generation, but the replacement of single exposure high-NA (0.55) over double patterning with standard EUV (NA = 0.33) depends on whether it provides better results at a reasonable cost per wafer.

Quick links to more news:

Global
In-Depth
Market Reports and Earnings
Education and Training
Security
Product News
Research
Events and Further Reading

Global

Belgium-based Imec released part 2 of its chiplets series, addressing testing strategies and standardization efforts, as well as guidelines and research “towards efficient ESD protection strategies for advanced 3D systems-on-chip.”

Also in Belgium, BelGan, maker of GaN chips, filed for bankruptcy according to the Brussels Times.

TSMC‘s Dresden, Germany, plant will break ground this month.

The UK will dole out more than £100 million (~US $128 million) in funding to develop five new quantum research hubs in Glasgow, Edinburgh, Birmingham, Oxford, and London.

MassPhoton is opening Hong Kong‘s first ultra-high vacuum GaN epitaxial wafer pilot line and will establish a GaN research center.

Infineon completed the sale of its manufacturing sites in the Philippines and South Korea to ASE.

Israel-based RAAAM Memory Technologies received a €5.25 million grant from the European Innovation Council (EIC) to support the development and commercialization of its innovative memory solutions. This funding will enable RAAAM to advance its research in high-performance and energy-efficient memory technologies, accelerating their integration into various applications and markets.

In-Depth

Semiconductor Engineering published its Automotive, Security and Pervasive Computing newsletter this week, featuring these top stories and video:

• Chip Security Now Depends On Widening Supply Chain
• Defining Chip Threat Models To Determining Security Risks
• Post-Quantum Computing Threatens Fundamental Transport Protocols

And:

• Where Power Savings Really Count
• Making Electronics More Efficient (video)

Market Reports and Earnings

The semiconductor equipment industry is on a positive trajectory in 2024, with moderate revenue growth observed in Q2 after a subdued Q1, according to a new report from Yole Group. Wafer Fab Equipment revenue is projected to grow by 1.3% year-on-year, despite a 12% drop in Q1. Test equipment lead times are normalizing, improving order conditions. Key areas driving growth include memory and logic capital expenditures and high-bandwidth memory demand.

Worldwide silicon wafer shipments increased by 7% in Q2 2024, according to SEMI‘s latest report. This growth is attributed to robust demand from multiple semiconductor sectors, driven by advancements in AI, 5G, and automotive technologies.

The RF GaN market is projected to grow to US $2 billion by 2029, a 10% CAGR, according to Yole Group.

Counterpoint released their Q2 smartphone top 10 report.

Renesas completed their acquisition of EDA firm Altium, best known for its EDA platform and freeware CircuitMaker package.

It’s earnings season and here are recently released financials in the chip industry:

AMD  Advantest   Amkor   Ansys  Arteris   Arm   ASE   ASM   ASML
Cadence  IBM   Intel   Lam Research   Lattice   Nordson   NXP   Onsemi 
Qualcomm   Rambus  Samsung    SK Hynix   STMicro   Teradyne    TI  
Tower  TSMC    UMC  Western Digital

Industry stock price impacts are here.

Education and Training

Rochester Institute of Technology is leading a new pilot program to prepare community college students in areas such as cleanroom operations, new materials, simulation, and testing processes, with the intent of eventual transfer into RIT’s microelectronic engineering program.

Purdue University inked a deal with three research institutions — University of Piraeus, Technical University of Crete, and King’s College London —to develop joint research programs for semiconductors, AI and other critical technology fields.

The European Chips Skills Academy formed the Educational Leaders Board to help bridge the talent gap in Europe’s microelectronics sector.  The Board includes representatives from universities, vocational training providers, educators and research institutions who collaborate on strategic initiatives to strengthen university networks and build academic expertise through ECSA training programs.

Security

The Cybersecurity and Infrastructure Security Agency (CISA) is encouraging Apple users to review and apply this week’s recent security updates.

Microsoft Azure experienced a nearly 10 hour DDoS attack this week, leading to global service disruption for many customers.  “While the initial trigger event was a Distributed Denial-of-Service (DDoS) attack, which activated our DDoS protection mechanisms, initial investigations suggest that an error in the implementation of our defenses amplified the impact of the attack rather than mitigating it,” stated Microsoft in a release.

NIST published:

• “Recommendations For Increasing U.S. Participation and Leadership in Standards Development,” a report outlining cybersecurity recommendations and mitigation strategies.
• Final guidance documents and software to help improve the “safety, security and trustworthiness of AI systems.”
• Cloud Computing Forensic Reference Architecture guide.

Delta Air Lines plans to seek damages after losing $500 million in lost revenue due to security company CrowdStrike‘s software update debacle.  And shareholders are also angry.

Recent security research:

• Physically Secure Logic Locking With Nanomagnet Logic (UT Dallas)
• WBP: Training-time Backdoor Attacks through HW-based Weight Bit Poisoning (UCF)
• S-Tune: SOT-MTJ Manufacturing Parameters Tuning for Secure Next Generation of Computing ( U. of Arizona, UCF)
• Diffie Hellman Picture Show: Key Exchange Stories from Commercial VoWiFi Deployments (CISPA, SBA Research, U. of Vienna)

Product News

Lam Research introduced a new version of its cryogenic etch technology designed to enhance the manufacturing of 3D NAND for AI applications. This technology allows for the precise etching of high aspect ratio features, crucial for creating 1,000-layer 3D NAND.

Fig.1: 3D NAND etch. Source: Lam Research

Alphawave Semi launched its Universal Chiplet Interconnect Express Die-toDie IP. The subsystem offers 8 Tbps/mm bandwidth density and supports operation at 24 Gbps for D2D connectivity.

Infineon introduced a new MCU series for industrial and consumer motor controls, as well as power conversion system applications. The company also unveiled its new GoolGaN Drive product family of integrated single switches and half-bridges with integrated drivers.

Rambus released its DDR5 Client Clock Driver for next-gen, high-performance desktops and notebooks. The chips include Gen1 to Gen4 RCDs, power management ICs, Serial Presence Detect Hubs, and temperature sensors for leading-edge servers.

SK hynix introduced its new GDDR7 graphics DRAM. The product has an operating speed of 32Gbps, can process 1.5TB of data per second and has a 50% power efficiency improvement compared to the previous generation.

Intel launched its new Lunar Lake Ultra processors. The long awaited chips will be included in more than 80 laptop designs and has more than 40 NPU tera operations per second as well as over 60 GPU TOPS delivering more than 100 platform TOPS.

Brewer Science achieved recertification as a Certified B Corporation, reaffirming its commitment to sustainable and ethical business practices.

Panasonic adopted Siemens’ Teamcenter X cloud product lifecycle management solution, citing Teamcenter X’s Mendix low-code platform, improved operational efficiency and flexibility for its choice.

Keysight validated its 5G NR FR1 1024-QAM demodulation test cases for the first time. The 5G NR radio access technology supports eMBB and was validated on the 3GPP TS 38.521-4 test specification.

Research

In a 47-page deep-dive report, the Center for Security and Emerging Technology delved into all of the scientific breakthroughs from 1980 to present that brought EUV lithography to commercialization, including lessons learned for the next emerging technologies.

Researchers at the Paul Scherrer Institute developed a high-performance X-ray tomography technique using burst ptychography, achieving a resolution of 4nm. This method allows for non-destructive imaging of integrated circuits, providing detailed views of nanostructures in materials like silicon and metals.

MIT signed a four-year agreement with the Novo Nordisk Foundation Quantum Computing Programme at University of Copenhagen, focused on accelerating quantum computing hardware research.

MIT’s Research Laboratory of Electronics (RLE) developed a mechanically flexible wafer-scale integrated photonics fabrication platform. This enables the creation of flexible photonic circuits that maintain high performance while being bendable and stretchable. It offers significant potential for integrating photonic circuits into various flexible substrate applications in wearable technology, medical devices, and flexible electronics.

The Naval Research Lab identified a new class of semiconductor nanocrystals with bright ground-state excitons, emphasizing an important advancement in optoelectronics.

Researchers from National University of Singapore developed a novel method, known as tension-driven CHARM3D,  to fabricate 3D self-healing circuits, enabling the 3D printing of free-standing metallic structures without the need for support materials and external pressure.

Find more research in our Technical Papers library.

Events and Further Reading

Find upcoming chip industry events here, including:

Upcoming webinars are here, including topics such as quantum safe cryptography, analytics for high-volume manufacturing, and mastering EMC simulations for electronic design.

Find Semiconductor Engineering’s latest newsletters here:

Automotive, Security and Pervasive Computing
Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials

The post Chip Industry Week in Review appeared first on Semiconductor Engineering.

Data management is becoming a significant new challenge for the chip industry, as well as a brand new opportunity, as the amount of data collected at every step of design through manufacturing continues to grow.

Exacerbating the problem is the rising complexity of designs, many of which are highly customized and domain-specific at the leading edge, as well as increasing demands for reliability and traceability. There also is a growing focus on chiplets developed using different processes, including some from different foundries, and new materials such as glass substrates and ruthenium interconnects. On the design side, EDA and verification tools can generate terabytes of data on a weekly or even a daily basis, unlike in the past when this was largely done on a per-project basis.

While more data can be used to provide insights into processes and enable better designs, it’s an ongoing challenge to manage the current volumes being generated. The entire industry must rethink some well-proven methodologies and processes, as well as invest in a variety of new tools and approaches. At the same time, these changes are generating concern in an industry used to proceeding cautiously, one step at a time, based on silicon- and field-proven strategies. Increasingly, AI/ML is being added into design tools to identify anomalies and patterns in large data sets, and many of those tools are being regularly updated as algorithms are updated and new features are added, making it difficult to know exactly when and where to invest, which data to focus on, and with whom to share it.

“Every company has its own design flow, and almost every company has its own methodology around harvesting that data, or best practices about what reports should or should not be written out at what point,” said Rob Knoth, product management director in Cadence’s Digital & Signoff group. “There’s a death by 1,000 cuts that can happen in terms of just generating titanic volumes of data because, in general, disk space is cheap. People don’t think about it a lot, and they’ll just keep generating reports. The problem is that just because you’re generating reports doesn’t mean you’re using them.”

Fig. 1: Rising design complexity is driving increased need for data management. Source: IEEE Rising Stars 2022/Cadence

As with any problem in chip design, there is opportunity in figuring out a path forward. “You can always just not use the data, and then you’re back where you started,” said Tony Chan Carusone, CTO at Alphawave Semi. “The reason it becomes a problem for organizations is because they haven’t architected things from the beginning to be scalable, and therefore, to be able to handle all this data. Now, there’s an opportunity to leverage data, and it’s a different way. So it’s disruptive because you have to tear things apart, from re-architecting systems and processes to how you collect and store data, and organize it in order to take advantage of the opportunity.”

Buckets of data, buckets of problems
The challenges that come with this influx of data can be divided into three buckets, said Jim Schultz, senior staff product manager at Synopsys. The first is figuring out what information is actually critical to keep. “If you make a run, designers tend to save that run because if they need to do a follow up run, they have some data there and they may go, ‘Okay, well, what’s the runtime? How long did that run take, because my manager is going to ask me what I think the runtime is going to be on the next project or the next iteration of the block. While that data may not be necessary, designers and engineers have a tendency to hang onto it anyway, just in case.”

The second challenge is that once the data starts to pour in, it doesn’t stop, raising questions about how to manage collection. And third, once the data is collected, how can it be put to best use?

“Data analytics have been around with other types of companies exploring different types of data analytics, but the differences are those are can be very generic solutions,” said Schultz. “What we need for our industry is going to be very specific data analytics. If I have a timing issue, I want you to help me pinpoint what the cause of that timing violation is. That’s very specific to what we do in EDA. When we talk about who is cutting through the noise, we don’t want data that’s just presented. We want the data that is what the designer most cares about.”

Data security
The sheer number of tools being used and companies and people involved along the design pathway raises another challenge — security.

“There’s a lot of thought and investment going into the security aspect of data, and just as much as the problem of what data to save and store is the type of security we have to have without hindering the user day-to-day,” said Simon Rance, director of product management at Keysight. “That’s becoming a bigger challenge. Things like the CHIPS Act and the geopolitical scenarios we have at the moment are compounding that problem because a lot of the companies that used to create all these devices by themselves are having to collaborate, even with companies in different regions of the globe.”

This requires a balancing act. “It’s almost like a recording studio where you have all these knobs and dials to fine tune it, to make sure we have security of the data,” said Rance. “But we’re also able to get the job done as smoothly and as easily as we can.”

Further complicating the security aspect is that designing chips is not a one-man job. As leading-edge chips become increasingly complex and heterogeneous, they can involve hundreds of people in multiple companies.

“An important thing to consider when you’re talking about big data and analytics is what you’re going to share and with whom you’re going to share it,” said Synopsys’ Schultz. “In particular, when you start bringing in and linking data from different sources, if you start bringing in data related to silicon performance, you don’t want everybody to have access to that data. So the whole security protocol is important.”

Even the mundane matters — having a ton of data makes it likely, at some point, that data will be moved.

“The more places the data has to be transferred to, the more delays,” said Rance. “The bigger the data set, the longer it takes to go from A to B. For example, a design team in the U.S. may be designing during the day. Then, another team in Singapore or Japan will pick up on that design in their time zone, but they’re across the world. So you’re going to have to sync the data back and forth between these kinds of design sites. The bigger the data, the harder to sync.”

Solutions
The first step toward solving the issue of too much data is figuring out what data is actually needed. Rance said his team has found success using smart algorithms that help figure out which data is essential, which in turn can help optimize storage and transfer times.

There are less technical problems that can rear their heads, as well. Gina Jacobs, head of global communications and brand marketing at Arteris, said that engineers who use a set methodology — particularly those who are used to working on a problem by themselves and “brute forcing” a solution – also can find themselves overwhelmed by data.

“Engineers and designers can also switch jobs, taking with them institutional knowledge,” Jacobs said. “But all three problems can be solved with a single solution — having data stored in a standardized way that is easily accessible and sortable. It’s about taking data and requirements and specifications in different forms and then having it in the one place so that the different teams have access to it, and then being able to make changes so there is a single source of truth.”

Here, EDA design and data management tools are increasingly relying on artificial intelligence to help. Schultz forecasted a future where generative AI will touch every facet of chip development. “Along with that is the advanced data analytics that is able to mine all of that data you’ve been collecting, instead of going beyond the simple things that people have been doing, like predicting how long runtime is going to be or getting an idea what the performance is going to be,” he said. “Tools are going to be able to deal with all of that data and recognize trends much faster.”

Still, those all-encompassing AI tools, capable of complex analysis, are still years away. Cadence’s Knoth said he’s already encountered clients that are reluctant to bring it into the mix due to fears over the costs involved in disk space, compute resources, and licenses. Others, however, have been a bit more open-minded.

“Initially, AI can use a lot of processors to generate a lot of data because it’s doing a lot of things in parallel when it’s doing the inferencing, but it usually gets to the result faster and more predictably,” he said. So while a machine learning algorithm may generate even more vast amounts of data, on top of the piles currently available, “a good machine learning algorithm could be watching and smartly killing or restarting jobs where needed.”

As for the humans who are still an essential component to chip design, Alphawave’s Carusone said hardware engineers should take a page from lessons learned years ago from their counterparts in the software development world.

These include:

• Having an organized and automated way to collect data, file it in a repository, and not do anything manually;
• Developing ways to run verification and lab testing and everything in between in parallel, but with the data organized in a way that can be mined; and
• Creating methods for rigorously checking in and out of different test cases that you want to consider.

“The big thing is you’ve got all this data collected, but then what is each of each of those files, each of those collections of data?” said Carusone. “What does that correspond to? What test conditions was that collected in? The software community dealt with that a while ago, and the hardware community also needs to have this under its belt, taking it to the next level and recognizing we really need to be able to do this en masse. We need to be able to have dozens of people work in parallel, collecting data and have it all on there. We can test a big collection of our designs in the lab without anyone having to touch a thing, and then also try refinements of the firmware, scale them out, then have all the data come in and be analyzed. Being able to have all that done in an automated way lets you track down and fix problems a lot more quickly.”

Conclusion
The influx of new tools used to analyze and test chip designs has increased productivity, but those designs come with additional considerations. Institutions and individual engineers and designers have never had access to so much data, but that data is of limited value if it’s not used effectively.

Strategies to properly store and order that data are essential. Some powerful tools are already in place to help do that, and the AI revolution promises to make even more powerful resources available to quickly cut down on the time needed to run tests and analyze the results.

For now, handling all that data remains a tricky balance, according to Cadence’s Knoth. “If this was an easy problem, it wouldn’t be a problem. Being able to communicate effectively, hierarchically — not just from a people management perspective, but also hierarchically from a chip and project management perspective — is difficult. The teams that do this well invest resources into that process, specifically the communication of top-down tightening of budgets or top-down floorplan constraints. These are important to think about because every engineer is looking at chip-level timing reports, but the problem that they’re trying to solve might not ever be visible. But if they have a report that says, ‘Here is your view of what your problems are to solve,’ you can make some very effective work.”

Further Reading
EDA Pushes Deeper Into AI
AI is both evolutionary and revolutionary, making it difficult to assess where and how it will be used, and what problems may crop up.
Optimizing EDA Cloud Hardware And Workloads
Algorithms written for GPUs can slice simulation time from weeks to hours, but not everything is optimized or benefits equally.

The post AI For Data Management appeared first on Semiconductor Engineering.

Synopsys refocused its security priorities around chips, striking a deal to sell off its Software Integrity Group subsidiary to private equity firms Clearlake Capital Group and Francisco Partners for about $2.1 billion. That deal comes on the heels of Synopsys’ recent acquisition of Intrinsic ID, which develops physical unclonable function IP. Sassine Ghazi, Synopsys’ president and CEO, said in an interview that the sale of the software group “gives us the ability to have management bandwidth, capital, and to double down on what we’re doing in our core business.”

The U.S. Commerce Department reportedly pulled export licenses from Intel and Qualcomm that permitted them to ship semiconductors to Huawei, the Financial Times reported. The move comes after advanced chips from Intel reportedly were used in new laptops and smartphones from the China-based company. 

Apple debuted its second-generation 3nm M4 chip with the launch of the new iPad Pro. The CPU and GPU each have up to 10 cores, with a neural engine capable of 38 TOPS, and a total of 28 billion transistors. Apple also is working with TSMC to develop its own AI processors for running software in data centers, reports The Wall Street Journal.

The U.S. is expected to triple its semiconductor manufacturing capacity by 2032, according to a new report by the Semiconductor Industry Association and Boston Consulting. By that year, the U.S. is projected to have 28% of global capacity for advanced logic manufacturing and over a quarter of total global capital expenditures.

Fig. 1: Source: Semiconductor Industry Association and Boston Consulting Group.

Quick links to more news:

Global
Market Reports
Automotive
Security
Product News
Education and Training
Research
In-Depth
Events
Further Reading

Around The Globe

The U.S. Commerce Department plans to solicit bids from organizations interested in creating and managing a new CHIPS Manufacturing USA institute focused on digital twins in the semiconductor sector. The government will award up to $285 million to the selected proposal.

The U.S. National Science Foundation and Department of Energy announced the first 35 projects to be supported with computational time through the National Artificial Intelligence Research Resource (NAIRR) Pilot. The initial selected projects will gain access to several U.S. supercomputing centers and other resources, with the goal of advancing responsible AI research.

Through its new Federal AI Sandbox, MITRE is offering up its computing power to U.S. government agencies. “Our new Federal AI Sandbox will help level the playing field, making the high-quality compute power needed to train and test custom AI solutions available to any agency,” stated Charles Clancy, MITRE, senior vice president and chief technology officer, in the release.

Saudi Arabia’s $100 billion investment fund for semiconductor and AI technology pledged it would divest from China if requested by the U.S, reported Bloomberg.

Japan’s SoftBank is holding talks with UK-based AI Chip firm Graphcore about a possible acquisition, reports Bloomberg.

India’s chip industry is heating up. Mindgrove launched the country’s first SoC, named Secure IoT. The chip clocks at 700 MHz, and the company is touting its key security algorithms, secure boot, and on-chip OTP memory. Meanwhile, Lam Research is expanding its global semiconductor fabrication supply chain to include India.

Microsoft will build a $3.3 billion AI data center in Racine, Wisconsin, the same location as the failed Foxconn investment touted six years ago.

Markets And Money

The SIA announced first-quarter global semiconductor sales grew more than 15% YoY, still 5.7% below Q4 2023, but a big improvement over last year. Consider that the semiconductor materials market contracted 8.2% in 2023 to $66.7 billion, down from a record $72.7 billion in 2022, according to a new report from SEMI.

The demand for AI-powered consumer electronics will drive global AI chipset shipments to 1.3 billion by 2030, according to ABI Research.

TrendForce released several new industry reports this week. Among the highlights:

• HBM prices are expected to increase by up to 10% in 2025, representing more than 30% of total DRAM value.
• In Q2, DRAM contract prices rose 13% to 18%, while NAND flash prices increased 15% to 20%.
• The top 10 design firms’ combined revenue increased 12% in 2023, with NVIDIA taking the lead for the first time.

A number of acquisitions were announced recently:

• High-voltage IC company, Power Integrations, will purchase the assets of Odyssey Semiconductor Technologies, a developer of gallium nitride (GaN) transistors.
• Mobix Labs agreed to buy RF design company RaGE Systems for $20 million in cash, stock, and incentives.
• V-Tek, a packaging services and inspection company, acquired A&J Programming, a manufacturer of automated handling and programming equipment.

The global smartphone market grew 6% year-over-year, shipping 296.9 million units in Q124, according to a Counterpoint report.  Samsung toppled Apple for the top spot with a 20% share.

Automotive

U.S. Justice Department is investigating whether Tesla committed securities or wire fraud for misleading consumers and investors about its EV’s autopilot capabilities, according to Reuters.

The automotive ecosystem is undergoing a huge transformation toward software-defined vehicles, spurring new architectures that can be future-proofed and customized with software.

Infineon introduced a microcontroller for the automotive battery management sector, integrating high-precision analog and high-voltage subsystems on a single chip. Infineon also inked a deal with China’s Xiaomi to provide SiC power modules for Xiaomi’s new SU7 smart EV.

Keysight and ETAS are teaming up to embed ETAS fuzz testing software into Keysight’s automotive cybersecurity platform.

Also, Keysight’s device security research lab, Riscure Security Solutions, can now conduct vehicle type approval evaluations under United Nations R155/R156 regulations. Keysight acquired Riscure in March.

Two autonomous driving companies received big funding. British AI company Wayve received a $1.05 billion Series C investment from SoftBank, with contributions from NVIDIA and Microsoft. Hyundai spent an additional $475 million on Motional, according its recent earnings report.

The automotive imaging market grew to U.S. $5.7 billion in 2023 due to increased production, autonomy demand, and higher-resolution offerings.

Automotive Grade Linux (AGL), a collaborative cross-industry effort developing an open source platform for all Software-Defined Vehicles (SDVs), released cloud-native functionality, RISC-V architecture and flutter applications.

Security

SRAM security concerns are intensifying as a combination of new and existing techniques allow hackers to tap into data for longer periods of time after a device is powered down. This is particularly alarming as the leading edge of design shifts to heterogeneous systems in package, where chiplets frequently have their own memory hierarchy.

Machine learning is being used by hackers to find weaknesses in chips and systems, but it also is starting to be used to prevent breaches by pinpointing hardware and software design flaws.

txOne Networks, provider of Cyber-Physical Systems security, raised $51 million in Series B extension round of funding.

The U.S. Department of Justice charged a Russian national with his role as the creator, developer and administrator of the LockBit, a prolific ramsomware group, that allegedly stole $100 million in payments from 2,000 victims.

The Cybersecurity and Infrastructure Security Agency (CISA) launched “We Can Secure Our World,” a new public awareness program promoting “basic cyber hygiene” and the agency also issues a number of alerts/advisories.

Product News

Siemens unveiled its Solido IP Validation Suite software, an automated quality assurance product designed to work across all design IP types and formats. The suite includes Solido Crosscheck and IPdelta software, which both provide in-view, cross-view and version-to-version QA checks.

proteanTecs announced its lifecycle monitoring solution is being integrated into SAPEON’s new AI processors.

SpiNNcloud Systems revealed their SpiNNaker2 system, an event-based AI platform supercomputer containing chips that are a mesh of 152 ARM-based cores. The platform has the ability to emulate 10 billion neurons while still maintaining power efficiency and reliability.

Ansys partnered with Schrodinger to develop new computational materials. The collaboration will see Schrodinger’s molecular modeling technology used in Ansys’ simulation tools to evaluate performance ahead of the prototype phase.

Keysight introduced a pulse generator to its handheld radio frequency analyzer software options. The Option 357 pulse generator is downloadable on B- and C-Series FieldFox analyzers.

Education and Training

Semiconductor fever is hitting academia:

• Penn State discussed its role in leading 15 universities to drive advances in chip integration and packaging.
• Georgia Tech’s explained its research is happening at all the levels of the “semiconductor stack,” touting its 28,500 square feet of academic cleanroom space.
• And in the past month Purdue University, Dassault Systems and Lam Research expanded an existing deal to use virtual twins and simulation tools in workforce development.

Arizona State University is beefing up their technology programs with a new bachelor’s and doctoral degree in robotics and autonomous systems.

Microsoft is partnering with Gateway Technical College in Wisconsin to create a Data Center Academy to train Wisconsinites for data center and STEM roles by 2030.

Research

Stanford-led researchers used ordinary-appearing glasses for an augmented reality headset, utilizing waveguide display techniques, holographic imaging, and AI.

UC Berkeley, LLNL, and MIT engineered a miniaturized on-chip energy storage and power delivery, using an atomic-scale approach to modify electrostatic capacitors.

ORNL and other researchers observed a “surprising isotope effect in the optoelectronic properties of a single layer of molybdenum disulfide” when they substituted heavier isotope of molybdenum in the crystal.

Three U.S. national labs are partnering with NVIDIA to develop advanced memory technologies for high performance computing.

In-Depth

In addition to this week’s Automotive, Security and Pervasive Computing newsletter, here are more top stories and tech talk from the week:

• Communication Is Key To Finding And Fixing Bugs In ICs
• Can Models Created With AI Be Trusted?
• Adapting To Evolving IC Requirements

Events

Find upcoming chip industry events here, including:

Upcoming webinars are here.

Further Reading

Read the latest special reports and top stories, or check out the latest newsletters:

Automotive, Security and Pervasive Computing
Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials

The post Chip Industry Week In Review appeared first on Semiconductor Engineering.

Machine learning is being used by hackers to find weaknesses in chips and systems, but it also is starting to be used to prevent breaches by pinpointing hardware and software design flaws.

To make this work, machine learning (ML) must be trained to identify vulnerabilities, both in hardware and software. With proper training, ML can detect cyber threats and prevent them from accessing critical data. As ML encounters additional cyberattack scenarios, it can learn and adapt, helping to build a more sophisticated defense system that includes hardware, software, and how they interface with larger systems. It also can automate many cyber defense tasks with minimum human intervention, which saves time, effort, and money.

ML is capable of sifting through large volumes of data much faster than humans. Potentially, it can reduce or remove human errors, lower costs, and boost cyber defense capability and overall efficiency. It also can perform such tasks as connection authentication, system design, vulnerability detection, and most important, threat detection through pattern and behavioral analysis.

“AI/ML is finding many roles protecting and enhancing security for digital devices and services,” said David Maidment, senior director of market development at Arm. “However, it is also being used as a tool for increasingly sophisticated attacks by threat actors. AI/ML is essentially a tool tuned for very advanced pattern recognition across vast data sets. Examples of how AI/ML can enhance security include network-based monitoring to spot rogue behaviors at scale, code analysis to look for vulnerabilities on new and legacy software, and automating the deployment of software to keep devices up-to-date and secure.”

This means that while AI/ML can be used as a force for good, inevitably bad actors will use it to increase the sophistication and scale of attacks. “Building devices and services based on security best practices, having a hardware-protected root of trust (RoT), and an industry-wide methodology to standardize and measure security are all essential,” Maidment said. “The focus on security, including the rapid growth of AI/ML, is certainly driving industry and government discussions as we work on solutions to maximize AI/ML’s benefits and minimize any potential harmful impact.”

Zero trust is a fundamental requirement when it comes to cybersecurity. Before a user or device is allowed to connect to the network or server, requests have to be authenticated to make sure they are legitimate and authorized. ML will enhance the authentication process, including password management, phishing prevention, and malware detection.

Areas that bad actors look to exploit are software design vulnerabilities and weak points in systems and networks. Once hackers uncover these vulnerabilities, they can be used as a point of entrance to the network or systems. ML can detect these vulnerabilities and alert administrators.

Taking a proactive approach by doing threat detection is essential in cyber defense. ML pattern and behavioral analysis strengths support this strategy. When ML detects unusual behavior in data traffic flow or patterns, it sends an alert about abnormal behavior to the administrator. This is similar to the banking industry’s practice of watching for credit card use that does not follow an established pattern. A large purchase overseas on a credit card with a pattern of U.S. use only for moderate amounts would trigger an alert, for example.

As hackers become more sophisticated with new attack vectors, whether it is new ransomware or distributed denial of service (DDoS) attacks, ML will do a much better job than humans in detecting these unknown threats.

Limitations of ML in cybersecurity
While ML provides many benefits, its value depends on the data used to train it. The more that can be used to train the ML model, the better it is at detecting fraud and cyber threats. But acquiring this data raises overall cybersecurity system design expenses. The model also needs constant maintenance and tuning to sustain peak performance and meet the specific needs of users. And while ML can do many of the tasks, it still requires some human involvement, so it’s essential to understand both cybersecurity and how well ML functions.

While ML is effective in fending off many of the cyberattacks, it is not a panacea. “The specific type of artificial intelligence typically referenced in this context is machine learning (ML), which is the development of algorithms that can ingest large volumes of training data, then generalize and make meaningful observations and decisions based on novel data,” said Scott Register, vice president of security solutions at Keysight Technologies. “With the right algorithms and training, AI/ML can be used to pinpoint cyberattacks which might otherwise be difficult to detect.”

However, no one — at least in the commercial space — has delivered a product that can detect very subtle cyberattacks with complete accuracy. “The algorithms are getting better all the time, so it’s highly probable that we’ll soon have commercial products that can detect and respond to attacks,” Register said. “We must keep in mind, however, that attackers don’t sit still, and they’re well-funded and patient. They employ ‘offensive AI,’ which means they use the same types of techniques and algorithms to generate attacks which are unlikely to be detected.”

ML implementation considerations
For any ML implementation, a strong cyber defense system is essential, but there’s no such thing as a completely secure design. Instead, security is a dynamic and ongoing process that requires constant fine-tuning and improvement against ever-changing cyberattacks. Implementing ML requires a clear security roadmap, which should define requirements. It also requires implementing a good cybersecurity process, which secures individual hardware and software components, as well as some type of system testing.

“One of the things we advise is to start with threat modeling to identify a set of critical design assets to protect from an adversary under confidentiality or integrity,” said Jason Oberg, CTO at Cycuity. “From there, you can define a set of very succinct, secure requirements for the assets. All of this work is typically done at the architecture level. We do provide education, training and guidance to our customers, because at that level, if you don’t have succinct security requirements defined, then it’s really hard to verify or check something in the design. What often happens is customers will say, ‘I want to have a secure chip.’ But it’s not as easy as just pressing a button and getting a green check mark that confirms the chip is now secure.”

To be successful, engineering teams must start at the architectural stages and define the security requirements. “Once that is done, they can start actually writing the RTL,” Oberg said. “There are tools available to provide assurances these security requirements are being met, and run within the existing simulation and emulation environments to help validate the security requirements, and help identify any unknown design weaknesses. Generally, this helps hardware and verification engineers increase their productivity and build confidence that the system is indeed meeting the security requirements.”

Fig. 1: A cybersecurity model includes multiple stages, progressing from the very basic to in-depth. It is important for organizations to know what stages their cyber defense system are. Source: Cycuity

Steve Garrison, senior vice president, marketing of Stellar Cyber, noted that if cyber threats were uncovered during the detection process, so many data files may be generated that they will be difficult for humans to sort through. Graphical displays can speed up the process and reduce the overall mean time to detection (MTTD) and mean time to response (MTTR).

Fig. 2: Using graphical displays  would reduce the overall meantime to detection (MTTD) and meantime to response (MTTR). Source: Stellar Cyber

Testing is essential
Another important stage in the design process is testing, whereby each system design requires a vigorous attack simulation tool to weed out the basic oversights to ensure it meets the predefined standard.

“First, if you want to understand how defensive systems will function in the real world, it’s important to test them under conditions, which are as realistic as possible,” Keysight’s Register said. “The network environment should have the same amount of traffic, mix of applications, speeds, behavioral characteristics, and timing as the real world. For example, the timing of a sudden uptick in email and social media traffic corresponds to the time when people open up their laptops at work. The attack traffic needs to be as realistic as possible as well – hackers try hard not to be noticed, often preferring ‘low and slow’ attacks, which may take hours or days to complete, making detection much more difficult. The same obfuscation techniques, encryption, and decoy traffic employed by threat actors needs to be simulated as accurately as possible.”

Further, due to mistaken assumptions during testing, defensive systems often perform great in the lab, yet fail spectacularly in production networks.  “Afterwards we hear, for example, ‘I didn’t think hackers would encrypt their malware,’ or ‘Internal e-mails weren’t checked for malicious attachments, only those from external senders,’” Register explained. “Also, in security testing, currency is key. Attacks and obfuscation techniques are constantly evolving. If a security system is tested against stale attacks, then the value of that testing is limited. The offensive tools should be kept as up to date as possible to ensure the most effective performance against the tools a system is likely to encounter in the wild.”

Semiconductor security
Almost all system designs depend on semiconductors, so it is important to ensure that any and all chips, firmware, FPGAs, and SoCs are secure – including those that perform ML functionality.

“Semiconductor security is a constantly evolving problem and requires an adaptable solution, said Jayson Bethurem, vice president marketing and business development at Flex Logix. “Fixed solutions with current cryptography that are implemented today will inevitably be challenged in the future. Hackers today have more time, resources, training, and motivation to disrupt technology. With technology increasing in every facet of our lives, defending against this presents a real challenge. We also have to consider upcoming threats, namely quantum computing.”

Many predict that quantum computing will be able to crack current cryptography solutions in the next few years. “Fortunately, semiconductor manufacturers have solutions that can enable cryptography agility, which can dynamically adapt to evolving threats,” Bethurem said. “This includes both updating hardware accelerated cryptography algorithms and obfuscating them, an approach that increases root of trust and protects valuable IP secrets. Advanced solutions like these also involve devices randomly creating their own encryption keys, making it harder for algorithms to crack encryption codes.”

Advances in AI/ML algorithms can adapt to new threats and reduce latency of algorithm updates from manufacturers. This is particularly useful with reconfigurable eFPGA IP, which can be implemented into any semiconductor device to thwart all current and future threats and optimized to run AI/ML-based cryptography solutions. The result is a combination of high-performance processing, scalability, and low-latency attack response.

Chips that support AI/ML algorithms need not only computing power, but also accelerators for those algorithms. In addition, all of this needs to happen without exceeding a tight power budget.

“More AI/ML systems run at tiny edges rather than at the core,” said Detlef Houdeau, senior director of design system architecture at Infineon Technologies. “AI/ML systems don’t need any bigger computer and/or cloud. For instance, a Raspberry Pi for a robot in production can have more than 3 AI/ML algorithms working in parallel. A smartphone has more than 10 AI/ML functions in the phone, and downloading new apps brings new AI/ML algorithms into the device. A pacemaker can have 2 AI/ML algorithms. Security chips, meanwhile, need a security architecture as well as accelerators for encryption. Combining an AI/ML accelerator with an encryption accelerator in the same chip could increase the performance in microcontroller units, and at the same time foster more security at the edge. The next generation of microelectronics could show this combination.”

After developers have gone through design reviews and the systems have run vigorous tests, it helps to have third-party certification and/or credentials to ensure the systems are indeed secure from a third-party independent viewpoint.

“As AI, and recently generative AI, continue to transform all markets, there will be new attack vectors to mitigate against,” said Arm’s Maidment. “We expect to see networks become smarter in the way they monitor traffic and behaviors. The use of AI/ML allows network-based monitoring at scale to allow potential unexpected or rogue behavior to be identified and isolated. Automating network monitoring based on AI/ML will allow an extra layer of defense as networks scale out and establish effectively a ‘zero trust’ approach. With this approach, analysis at scale can be tuned to look at particular threat vectors depending on the use case.”

With an increase in AI/ML adoption at the edge, a lot of this is taking place on the CPU. “Whether it is handling workloads in their entirety, or in combination with a co-processor like a GPU or NPU, how applications are deployed across the compute resources needs to be secure and managed centrally within the edge AI/ML device,” Maidment said. “Building edge AI/ML devices based on a hardware root of trust is essential. It is critical to have privileged access control of what code is allowed to run where using a trusted memory management architecture. Arm continually invests in security, and the Armv9 architecture offers a number of new security features. Alongside architecture improvements, we continue to work in partnership with the industry on our ecosystem security framework and certification scheme, PSA Certified, which is based on a certified hardware RoT. This hardware base helps to improve the security of systems and fulfill the consumer expectation that as devices scale, they remain secure.”

Outlook
It is important to understand that threat actors will continue to evolve attacks using AI/ML. Experts suggest that to counter such attacks, organizations, institutions, and government agencies will have to continually improve defense strategies and capabilities, including AI/ML deployment.

AI/ML can be used as weapon from an attacker for industrial espionage and/or industrial sabotage, and stopping incursions will require a broad range of cyberattack prevention and detection tools, including AI/ML functionality for anomaly detection. But in general, hackers are almost always one step ahead.

According to Register, “the recurring cycle is: 1) hackers come out with a new tool or technology that lets them attack systems or evade detection more effectively; 2) those attacks cause enough economic damage that the industry responds and develops effective countermeasures; 3) the no-longer-new hacker tools are still employed effectively, but against targets that haven’t bothered to update their defenses; 4) hackers develop new offensive tools that are effective against the defensive techniques of high-value targets, and the cycle starts anew.”

Related Reading
Securing Chip Manufacturing Against Growing Cyber Threats
Suppliers are the number one risk, but reducing attacks requires industry-wide collaboration.
Data Center Security Issues Widen
The number and breadth of hardware targets is increasing, but older attack vectors are not going away. Hackers are becoming more sophisticated, and they have a big advantage.

The post Using AI/ML To Combat Cyberattacks appeared first on Semiconductor Engineering.

Synopsys refocused its security priorities around chips, striking a deal to sell off its Software Integrity Group subsidiary to private equity firms Clearlake Capital Group and Francisco Partners for about $2.1 billion. That deal comes on the heels of Synopsys’ recent acquisition of Intrinsic ID, which develops physical unclonable function IP. Sassine Ghazi, Synopsys’ president and CEO, said in an interview that the sale of the software group “gives us the ability to have management bandwidth, capital, and to double down on what we’re doing in our core business.”

The U.S. Commerce Department reportedly pulled export licenses from Intel and Qualcomm that permitted them to ship semiconductors to Huawei, the Financial Times reported. The move comes after advanced chips from Intel reportedly were used in new laptops and smartphones from the China-based company. 

Apple debuted its second-generation 3nm M4 chip with the launch of the new iPad Pro. The CPU and GPU each have up to 10 cores, with a neural engine capable of 38 TOPS, and a total of 28 billion transistors. Apple also is working with TSMC to develop its own AI processors for running software in data centers, reports The Wall Street Journal.

The U.S. is expected to triple its semiconductor manufacturing capacity by 2032, according to a new report by the Semiconductor Industry Association and Boston Consulting. By that year, the U.S. is projected to have 28% of global capacity for advanced logic manufacturing and over a quarter of total global capital expenditures.

Fig. 1: Source: Semiconductor Industry Association and Boston Consulting Group.

Quick links to more news:

Global
Market Reports
Automotive
Security
Product News
Education and Training
Research
In-Depth
Events
Further Reading

Around The Globe

The U.S. Commerce Department plans to solicit bids from organizations interested in creating and managing a new CHIPS Manufacturing USA institute focused on digital twins in the semiconductor sector. The government will award up to $285 million to the selected proposal.

The U.S. National Science Foundation and Department of Energy announced the first 35 projects to be supported with computational time through the National Artificial Intelligence Research Resource (NAIRR) Pilot. The initial selected projects will gain access to several U.S. supercomputing centers and other resources, with the goal of advancing responsible AI research.

Through its new Federal AI Sandbox, MITRE is offering up its computing power to U.S. government agencies. “Our new Federal AI Sandbox will help level the playing field, making the high-quality compute power needed to train and test custom AI solutions available to any agency,” stated Charles Clancy, MITRE, senior vice president and chief technology officer, in the release.

Saudi Arabia’s $100 billion investment fund for semiconductor and AI technology pledged it would divest from China if requested by the U.S, reported Bloomberg.

Japan’s SoftBank is holding talks with UK-based AI Chip firm Graphcore about a possible acquisition, reports Bloomberg.

India’s chip industry is heating up. Mindgrove launched the country’s first SoC, named Secure IoT. The chip clocks at 700 MHz, and the company is touting its key security algorithms, secure boot, and on-chip OTP memory. Meanwhile, Lam Research is expanding its global semiconductor fabrication supply chain to include India.

Microsoft will build a $3.3 billion AI data center in Racine, Wisconsin, the same location as the failed Foxconn investment touted six years ago.

Markets And Money

The SIA announced first-quarter global semiconductor sales grew more than 15% YoY, still 5.7% below Q4 2023, but a big improvement over last year. Consider that the semiconductor materials market contracted 8.2% in 2023 to $66.7 billion, down from a record $72.7 billion in 2022, according to a new report from SEMI.

The demand for AI-powered consumer electronics will drive global AI chipset shipments to 1.3 billion by 2030, according to ABI Research.

TrendForce released several new industry reports this week. Among the highlights:

• HBM prices are expected to increase by up to 10% in 2025, representing more than 30% of total DRAM value.
• In Q2, DRAM contract prices rose 13% to 18%, while NAND flash prices increased 15% to 20%.
• The top 10 design firms’ combined revenue increased 12% in 2023, with NVIDIA taking the lead for the first time.

A number of acquisitions were announced recently:

• High-voltage IC company, Power Integrations, will purchase the assets of Odyssey Semiconductor Technologies, a developer of gallium nitride (GaN) transistors.
• Mobix Labs agreed to buy RF design company RaGE Systems for $20 million in cash, stock, and incentives.
• V-Tek, a packaging services and inspection company, acquired A&J Programming, a manufacturer of automated handling and programming equipment.

The global smartphone market grew 6% year-over-year, shipping 296.9 million units in Q124, according to a Counterpoint report.  Samsung toppled Apple for the top spot with a 20% share.

Automotive

U.S. Justice Department is investigating whether Tesla committed securities or wire fraud for misleading consumers and investors about its EV’s autopilot capabilities, according to Reuters.

The automotive ecosystem is undergoing a huge transformation toward software-defined vehicles, spurring new architectures that can be future-proofed and customized with software.

Infineon introduced a microcontroller for the automotive battery management sector, integrating high-precision analog and high-voltage subsystems on a single chip. Infineon also inked a deal with China’s Xiaomi to provide SiC power modules for Xiaomi’s new SU7 smart EV.

Keysight and ETAS are teaming up to embed ETAS fuzz testing software into Keysight’s automotive cybersecurity platform.

Also, Keysight’s device security research lab, Riscure Security Solutions, can now conduct vehicle type approval evaluations under United Nations R155/R156 regulations. Keysight acquired Riscure in March.

Two autonomous driving companies received big funding. British AI company Wayve received a $1.05 billion Series C investment from SoftBank, with contributions from NVIDIA and Microsoft. Hyundai spent an additional $475 million on Motional, according its recent earnings report.

The automotive imaging market grew to U.S. $5.7 billion in 2023 due to increased production, autonomy demand, and higher-resolution offerings.

Automotive Grade Linux (AGL), a collaborative cross-industry effort developing an open source platform for all Software-Defined Vehicles (SDVs), released cloud-native functionality, RISC-V architecture and flutter applications.

Security

SRAM security concerns are intensifying as a combination of new and existing techniques allow hackers to tap into data for longer periods of time after a device is powered down. This is particularly alarming as the leading edge of design shifts to heterogeneous systems in package, where chiplets frequently have their own memory hierarchy.

Machine learning is being used by hackers to find weaknesses in chips and systems, but it also is starting to be used to prevent breaches by pinpointing hardware and software design flaws.

txOne Networks, provider of Cyber-Physical Systems security, raised $51 million in Series B extension round of funding.

The U.S. Department of Justice charged a Russian national with his role as the creator, developer and administrator of the LockBit, a prolific ramsomware group, that allegedly stole $100 million in payments from 2,000 victims.

The Cybersecurity and Infrastructure Security Agency (CISA) launched “We Can Secure Our World,” a new public awareness program promoting “basic cyber hygiene” and the agency also issues a number of alerts/advisories.

Product News

Siemens unveiled its Solido IP Validation Suite software, an automated quality assurance product designed to work across all design IP types and formats. The suite includes Solido Crosscheck and IPdelta software, which both provide in-view, cross-view and version-to-version QA checks.

proteanTecs announced its lifecycle monitoring solution is being integrated into SAPEON’s new AI processors.

SpiNNcloud Systems revealed their SpiNNaker2 system, an event-based AI platform supercomputer containing chips that are a mesh of 152 ARM-based cores. The platform has the ability to emulate 10 billion neurons while still maintaining power efficiency and reliability.

Ansys partnered with Schrodinger to develop new computational materials. The collaboration will see Schrodinger’s molecular modeling technology used in Ansys’ simulation tools to evaluate performance ahead of the prototype phase.

Keysight introduced a pulse generator to its handheld radio frequency analyzer software options. The Option 357 pulse generator is downloadable on B- and C-Series FieldFox analyzers.

Education and Training

Semiconductor fever is hitting academia:

• Penn State discussed its role in leading 15 universities to drive advances in chip integration and packaging.
• Georgia Tech’s explained its research is happening at all the levels of the “semiconductor stack,” touting its 28,500 square feet of academic cleanroom space.
• And in the past month Purdue University, Dassault Systems and Lam Research expanded an existing deal to use virtual twins and simulation tools in workforce development.

Arizona State University is beefing up their technology programs with a new bachelor’s and doctoral degree in robotics and autonomous systems.

Microsoft is partnering with Gateway Technical College in Wisconsin to create a Data Center Academy to train Wisconsinites for data center and STEM roles by 2030.

Research

Stanford-led researchers used ordinary-appearing glasses for an augmented reality headset, utilizing waveguide display techniques, holographic imaging, and AI.

UC Berkeley, LLNL, and MIT engineered a miniaturized on-chip energy storage and power delivery, using an atomic-scale approach to modify electrostatic capacitors.

ORNL and other researchers observed a “surprising isotope effect in the optoelectronic properties of a single layer of molybdenum disulfide” when they substituted heavier isotope of molybdenum in the crystal.

Three U.S. national labs are partnering with NVIDIA to develop advanced memory technologies for high performance computing.

In-Depth

In addition to this week’s Automotive, Security and Pervasive Computing newsletter, here are more top stories and tech talk from the week:

• Communication Is Key To Finding And Fixing Bugs In ICs
• Can Models Created With AI Be Trusted?
• Adapting To Evolving IC Requirements

Events

Find upcoming chip industry events here, including:

Upcoming webinars are here.

Further Reading

Read the latest special reports and top stories, or check out the latest newsletters:

Automotive, Security and Pervasive Computing
Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials

The post Chip Industry Week In Review appeared first on Semiconductor Engineering.

Machine learning is being used by hackers to find weaknesses in chips and systems, but it also is starting to be used to prevent breaches by pinpointing hardware and software design flaws.

To make this work, machine learning (ML) must be trained to identify vulnerabilities, both in hardware and software. With proper training, ML can detect cyber threats and prevent them from accessing critical data. As ML encounters additional cyberattack scenarios, it can learn and adapt, helping to build a more sophisticated defense system that includes hardware, software, and how they interface with larger systems. It also can automate many cyber defense tasks with minimum human intervention, which saves time, effort, and money.

ML is capable of sifting through large volumes of data much faster than humans. Potentially, it can reduce or remove human errors, lower costs, and boost cyber defense capability and overall efficiency. It also can perform such tasks as connection authentication, system design, vulnerability detection, and most important, threat detection through pattern and behavioral analysis.

“AI/ML is finding many roles protecting and enhancing security for digital devices and services,” said David Maidment, senior director of market development at Arm. “However, it is also being used as a tool for increasingly sophisticated attacks by threat actors. AI/ML is essentially a tool tuned for very advanced pattern recognition across vast data sets. Examples of how AI/ML can enhance security include network-based monitoring to spot rogue behaviors at scale, code analysis to look for vulnerabilities on new and legacy software, and automating the deployment of software to keep devices up-to-date and secure.”

This means that while AI/ML can be used as a force for good, inevitably bad actors will use it to increase the sophistication and scale of attacks. “Building devices and services based on security best practices, having a hardware-protected root of trust (RoT), and an industry-wide methodology to standardize and measure security are all essential,” Maidment said. “The focus on security, including the rapid growth of AI/ML, is certainly driving industry and government discussions as we work on solutions to maximize AI/ML’s benefits and minimize any potential harmful impact.”

Zero trust is a fundamental requirement when it comes to cybersecurity. Before a user or device is allowed to connect to the network or server, requests have to be authenticated to make sure they are legitimate and authorized. ML will enhance the authentication process, including password management, phishing prevention, and malware detection.

Areas that bad actors look to exploit are software design vulnerabilities and weak points in systems and networks. Once hackers uncover these vulnerabilities, they can be used as a point of entrance to the network or systems. ML can detect these vulnerabilities and alert administrators.

Taking a proactive approach by doing threat detection is essential in cyber defense. ML pattern and behavioral analysis strengths support this strategy. When ML detects unusual behavior in data traffic flow or patterns, it sends an alert about abnormal behavior to the administrator. This is similar to the banking industry’s practice of watching for credit card use that does not follow an established pattern. A large purchase overseas on a credit card with a pattern of U.S. use only for moderate amounts would trigger an alert, for example.

As hackers become more sophisticated with new attack vectors, whether it is new ransomware or distributed denial of service (DDoS) attacks, ML will do a much better job than humans in detecting these unknown threats.

Limitations of ML in cybersecurity
While ML provides many benefits, its value depends on the data used to train it. The more that can be used to train the ML model, the better it is at detecting fraud and cyber threats. But acquiring this data raises overall cybersecurity system design expenses. The model also needs constant maintenance and tuning to sustain peak performance and meet the specific needs of users. And while ML can do many of the tasks, it still requires some human involvement, so it’s essential to understand both cybersecurity and how well ML functions.

While ML is effective in fending off many of the cyberattacks, it is not a panacea. “The specific type of artificial intelligence typically referenced in this context is machine learning (ML), which is the development of algorithms that can ingest large volumes of training data, then generalize and make meaningful observations and decisions based on novel data,” said Scott Register, vice president of security solutions at Keysight Technologies. “With the right algorithms and training, AI/ML can be used to pinpoint cyberattacks which might otherwise be difficult to detect.”

However, no one — at least in the commercial space — has delivered a product that can detect very subtle cyberattacks with complete accuracy. “The algorithms are getting better all the time, so it’s highly probable that we’ll soon have commercial products that can detect and respond to attacks,” Register said. “We must keep in mind, however, that attackers don’t sit still, and they’re well-funded and patient. They employ ‘offensive AI,’ which means they use the same types of techniques and algorithms to generate attacks which are unlikely to be detected.”

ML implementation considerations
For any ML implementation, a strong cyber defense system is essential, but there’s no such thing as a completely secure design. Instead, security is a dynamic and ongoing process that requires constant fine-tuning and improvement against ever-changing cyberattacks. Implementing ML requires a clear security roadmap, which should define requirements. It also requires implementing a good cybersecurity process, which secures individual hardware and software components, as well as some type of system testing.

“One of the things we advise is to start with threat modeling to identify a set of critical design assets to protect from an adversary under confidentiality or integrity,” said Jason Oberg, CTO at Cycuity. “From there, you can define a set of very succinct, secure requirements for the assets. All of this work is typically done at the architecture level. We do provide education, training and guidance to our customers, because at that level, if you don’t have succinct security requirements defined, then it’s really hard to verify or check something in the design. What often happens is customers will say, ‘I want to have a secure chip.’ But it’s not as easy as just pressing a button and getting a green check mark that confirms the chip is now secure.”

To be successful, engineering teams must start at the architectural stages and define the security requirements. “Once that is done, they can start actually writing the RTL,” Oberg said. “There are tools available to provide assurances these security requirements are being met, and run within the existing simulation and emulation environments to help validate the security requirements, and help identify any unknown design weaknesses. Generally, this helps hardware and verification engineers increase their productivity and build confidence that the system is indeed meeting the security requirements.”

Fig. 1: A cybersecurity model includes multiple stages, progressing from the very basic to in-depth. It is important for organizations to know what stages their cyber defense system are. Source: Cycuity

Steve Garrison, senior vice president, marketing of Stellar Cyber, noted that if cyber threats were uncovered during the detection process, so many data files may be generated that they will be difficult for humans to sort through. Graphical displays can speed up the process and reduce the overall mean time to detection (MTTD) and mean time to response (MTTR).

Fig. 2: Using graphical displays  would reduce the overall meantime to detection (MTTD) and meantime to response (MTTR). Source: Stellar Cyber

Testing is essential
Another important stage in the design process is testing, whereby each system design requires a vigorous attack simulation tool to weed out the basic oversights to ensure it meets the predefined standard.

“First, if you want to understand how defensive systems will function in the real world, it’s important to test them under conditions, which are as realistic as possible,” Keysight’s Register said. “The network environment should have the same amount of traffic, mix of applications, speeds, behavioral characteristics, and timing as the real world. For example, the timing of a sudden uptick in email and social media traffic corresponds to the time when people open up their laptops at work. The attack traffic needs to be as realistic as possible as well – hackers try hard not to be noticed, often preferring ‘low and slow’ attacks, which may take hours or days to complete, making detection much more difficult. The same obfuscation techniques, encryption, and decoy traffic employed by threat actors needs to be simulated as accurately as possible.”

Further, due to mistaken assumptions during testing, defensive systems often perform great in the lab, yet fail spectacularly in production networks.  “Afterwards we hear, for example, ‘I didn’t think hackers would encrypt their malware,’ or ‘Internal e-mails weren’t checked for malicious attachments, only those from external senders,’” Register explained. “Also, in security testing, currency is key. Attacks and obfuscation techniques are constantly evolving. If a security system is tested against stale attacks, then the value of that testing is limited. The offensive tools should be kept as up to date as possible to ensure the most effective performance against the tools a system is likely to encounter in the wild.”

Semiconductor security
Almost all system designs depend on semiconductors, so it is important to ensure that any and all chips, firmware, FPGAs, and SoCs are secure – including those that perform ML functionality.

“Semiconductor security is a constantly evolving problem and requires an adaptable solution, said Jayson Bethurem, vice president marketing and business development at Flex Logix. “Fixed solutions with current cryptography that are implemented today will inevitably be challenged in the future. Hackers today have more time, resources, training, and motivation to disrupt technology. With technology increasing in every facet of our lives, defending against this presents a real challenge. We also have to consider upcoming threats, namely quantum computing.”

Many predict that quantum computing will be able to crack current cryptography solutions in the next few years. “Fortunately, semiconductor manufacturers have solutions that can enable cryptography agility, which can dynamically adapt to evolving threats,” Bethurem said. “This includes both updating hardware accelerated cryptography algorithms and obfuscating them, an approach that increases root of trust and protects valuable IP secrets. Advanced solutions like these also involve devices randomly creating their own encryption keys, making it harder for algorithms to crack encryption codes.”

Advances in AI/ML algorithms can adapt to new threats and reduce latency of algorithm updates from manufacturers. This is particularly useful with reconfigurable eFPGA IP, which can be implemented into any semiconductor device to thwart all current and future threats and optimized to run AI/ML-based cryptography solutions. The result is a combination of high-performance processing, scalability, and low-latency attack response.

Chips that support AI/ML algorithms need not only computing power, but also accelerators for those algorithms. In addition, all of this needs to happen without exceeding a tight power budget.

“More AI/ML systems run at tiny edges rather than at the core,” said Detlef Houdeau, senior director of design system architecture at Infineon Technologies. “AI/ML systems don’t need any bigger computer and/or cloud. For instance, a Raspberry Pi for a robot in production can have more than 3 AI/ML algorithms working in parallel. A smartphone has more than 10 AI/ML functions in the phone, and downloading new apps brings new AI/ML algorithms into the device. A pacemaker can have 2 AI/ML algorithms. Security chips, meanwhile, need a security architecture as well as accelerators for encryption. Combining an AI/ML accelerator with an encryption accelerator in the same chip could increase the performance in microcontroller units, and at the same time foster more security at the edge. The next generation of microelectronics could show this combination.”

After developers have gone through design reviews and the systems have run vigorous tests, it helps to have third-party certification and/or credentials to ensure the systems are indeed secure from a third-party independent viewpoint.

“As AI, and recently generative AI, continue to transform all markets, there will be new attack vectors to mitigate against,” said Arm’s Maidment. “We expect to see networks become smarter in the way they monitor traffic and behaviors. The use of AI/ML allows network-based monitoring at scale to allow potential unexpected or rogue behavior to be identified and isolated. Automating network monitoring based on AI/ML will allow an extra layer of defense as networks scale out and establish effectively a ‘zero trust’ approach. With this approach, analysis at scale can be tuned to look at particular threat vectors depending on the use case.”

With an increase in AI/ML adoption at the edge, a lot of this is taking place on the CPU. “Whether it is handling workloads in their entirety, or in combination with a co-processor like a GPU or NPU, how applications are deployed across the compute resources needs to be secure and managed centrally within the edge AI/ML device,” Maidment said. “Building edge AI/ML devices based on a hardware root of trust is essential. It is critical to have privileged access control of what code is allowed to run where using a trusted memory management architecture. Arm continually invests in security, and the Armv9 architecture offers a number of new security features. Alongside architecture improvements, we continue to work in partnership with the industry on our ecosystem security framework and certification scheme, PSA Certified, which is based on a certified hardware RoT. This hardware base helps to improve the security of systems and fulfill the consumer expectation that as devices scale, they remain secure.”

Outlook
It is important to understand that threat actors will continue to evolve attacks using AI/ML. Experts suggest that to counter such attacks, organizations, institutions, and government agencies will have to continually improve defense strategies and capabilities, including AI/ML deployment.

AI/ML can be used as weapon from an attacker for industrial espionage and/or industrial sabotage, and stopping incursions will require a broad range of cyberattack prevention and detection tools, including AI/ML functionality for anomaly detection. But in general, hackers are almost always one step ahead.

According to Register, “the recurring cycle is: 1) hackers come out with a new tool or technology that lets them attack systems or evade detection more effectively; 2) those attacks cause enough economic damage that the industry responds and develops effective countermeasures; 3) the no-longer-new hacker tools are still employed effectively, but against targets that haven’t bothered to update their defenses; 4) hackers develop new offensive tools that are effective against the defensive techniques of high-value targets, and the cycle starts anew.”

Related Reading
Securing Chip Manufacturing Against Growing Cyber Threats
Suppliers are the number one risk, but reducing attacks requires industry-wide collaboration.
Data Center Security Issues Widen
The number and breadth of hardware targets is increasing, but older attack vectors are not going away. Hackers are becoming more sophisticated, and they have a big advantage.

The post Using AI/ML To Combat Cyberattacks appeared first on Semiconductor Engineering.

Samsung and Synopsys collaborated on the first production tapeout of a high-performance mobile SoC design, including CPUs and GPUs, using the Synopsys.ai EDA suite on Samsung Foundry’s gate-all-around (GAA) process. Samsung plans to begin mass production of 2nm process GAA chips in 2025, reports BusinessKorea.

UMC developed the first radio frequency silicon on insulator (RF-SOI)-based 3D IC process for chips used in smartphones and other 5G/6G mobile devices. The process uses wafer-to-wafer bonding technology to address radio frequency interference between stacked dies and reduces die size by 45%.

Fig. 1: UMC’s 3D IC solution for RFSOI technology. Source: UMC

The first programmable chip capable of shaping, splitting, and steering beams of light is now being produced by Skywater Technology and Lumotive. The technology is critical for advancing lidar-based systems used in robotics, automotive, and other 3D sensing applications.

Driven by demand for AI chips, SK hynix revealed it has already booked its entire production of high-bandwidth memory chips for 2024 and is nearly sold out of its production capacity for 2025, reported the Korea Times, while SEMI reported that silicon wafer shipments declined in Q1 2024, quarter over quarter, a 13% drop, attributed to continued weakness in IC fab utilization and inventory adjustments.

PCI-SIG published the CopprLink Internal and External Cable specifications to provide PCIe 5.0 and 6.0 signaling at 32 and 64 GT/s and leverage standard connector form factors for applications including storage, data centers, AI/ML, and disaggregated memory.

The U.S. Department of Commerce (DoC) launched the CHIPS Women in Construction Framework to boost the participation of women and economically disadvantaged people in the workforce, aiming to support on-time and successful completion of CHIPS Act-funded projects. Intel and Micron adopted the framework.

Quick links to more news:

Market Reports
Global
In-Depth
Education and Training
Security
Product News
Quantum
Research
Events
Further Reading

Markets and Money

The SiC wafer processing equipment market is growing rapidly, reports Yole. SiC devices will exceed $10B by 2029 at a CAGR of 25%, and the SiC manufacturing tool market is projected to reach $5B by 2026.

imec.xpand launched a €300 million (~$321 million) fund that will invest in semiconductor and nanotechnology startups with the potential to push semiconductor innovation beyond traditional applications and drive next-gen technologies.

Blaize raised $106 million for its programmable graph streaming processor architecture suite and low-code/no-code software platform for edge AI.

Guerrilla RF completed the acquisition of Gallium Semiconductor‘s portfolio of GaN power amplifiers and front-end modules.

About 90% of connected cars sold in 2030 will have embedded 5G capability, reported Counterpoint. Also, about 75% of laptop PCs sold in 2027 will be AI laptop PCs with advanced generative AI, and the global high-level OS (HLOS) or advanced smartwatch market is predicted to grow 15% in 2024.

Global

Powerchip Semiconductor opened a new 300mm facility in northwestern Taiwan targeting the production of AI semiconductors. The facility is expected to produce 50,000 wafers per month at 55, 40, and 28nm nodes.

Taiwan-based KYEC Semiconductor will withdraw its China operations by the third quarter due to increasing geopolitical tensions, reports the South China Morning Post.

Japan will expand its semiconductor export restrictions to China related to four technologies: Scanning electron microscopes, CMOS, FD-SOI, and the outputs of quantum computers, according to TrendForce.

IBM will invest CAD$187 million (~US$137M in Canada’s semiconductor industry, with the bulk of the investment focused on advanced assembly, testing, and packaging operations.

Microsoft will invest US$2.2 billion over the next four years to build Malaysia’s digital infrastructure, create AI skilling opportunities, establish an AI Center of Excellence, and enhance cybersecurity.

In-Depth

New stories and tech talks published by Semiconductor Engineering this week:

• Multi-Die Design Pushes Complexity To The Max
• Design Considerations In Photonics
• Overlay Optimization In Advanced IC Substrates
• Fundamental Issues In Computer Vision Still Unresolved
• Sensor Fusion Challenges In Automotive

Security

Infineon collaborated with ETAS to integrate the ESCRYPT CycurHSM 3.x automotive security software stack into its next-gen AURIX MCUs to optimize security, performance, and functionality.

Synopsys released Polaris Assist, an AI-powered application security assistant on its Polaris Software Integrity Platform, combining LLM technology with application security knowledge and intelligence.

In security research:

• UT Dallas, Intel, NXP, and TI published a framework for early anomaly detection in AMS components of automotive SoCs.
• The University of Central Florida said that LLMs can be harnessed to automatically rectify security-relevant vulnerabilities inherent in hardware designs within the semiconductor context.
• Western University leveraged hardware security modules for enhanced intra-domain security.
• A team in India proposed a post-quantum secure PUF-based cross-domain authentication mechanism for Internet of Drones.

U.S. President Biden signed a National Security Memorandum to enhance the resilience of critical infrastructure, and the White House announced key actions taken since Biden’s AI Executive Order, including measures to mitigate risk.

CISA and partners published a fact sheet on pro-Russia hacktivists who seek to compromise industrial control systems and small-scale operational technology systems in North American and European critical infrastructure sectors. CISA issued other alerts including two Microsoft vulnerabilities.

Education and Training

The U.S. National Institute for Innovation and Technology (NIIT) and the Department of Labor (DoL) partnered to celebrate the inaugural Youth Apprenticeship Week on May 5 to 11, highlighting opportunities in critical industries such as semiconductors and advanced manufacturing.

SUNY Poly received an additional $4 million from New York State for its Semiconductor Processing to Packaging Research, Education, and Training Center.

The University of Pennsylvania launched an online Master of Science in Engineering in AI degree.

The American University of Armenia celebrated its 10-year collaboration with Siemens, which provides AUA’s Engineering Research Center with annual research grants.

Product News

Renesas and SEGGER Embedded Studio launched integrated code generator support for its 32-bit RISC-V MCU. 

Rambus introduced a family of DDR5 server Power Management ICs (PMICs), including an extreme current device for high-performance applications.

Fig. 2: Rambus’ server PMIC on DDR5 RDIMM. Source: Rambus

Keysight added capabilities to Inspector, part of the company’s recently acquired device security research and test lab Riscure, that are designed to test the robustness of post-quantum cryptography (PQC) and help device and chip vendors identify and fix hardware vulnerabilities. Keysight also validated new conformance test cases for narrowband IoT non-terrestrial networks standards.

Ansys’ RedHawk-SC and Totem power integrity platforms were certified for TSMC‘s N2 nanosheet-based process technology, while its RaptorX solution for on-chip electromagnetic modeling was certified for TSMC’s N5 process.

Netherlands-based athleisure brand PREMIUM INC selected CLEVR to implement Siemens’ Mendix Digital Lifecycle Management for Fashion & Retail solution.

Micron will begin shipping high-capacity DRAM for AI data centers.

Microchip uncorked radiation-tolerant SoC FPGAs for space applications that uses a real-time Linux-capable RISC-V-based microprocessor subsystem.

Quantum

University of Chicago researchers developed a system to boost the efficiency of quantum error correction using a framework based on quantum low-density party-check (qLDPC) codes and new hardware involving reconfigurable atom arrays.

PsiQuantum will receive AUD $940 million (~$620 million) in equity, grants, and loans from the Australian and Queensland governments to deploy a utility-scale quantum computer in the regime of 1 million physical qubits in Brisbane, Australia.

Japan-based RIKEN will co-locate IBM’s Quantum System Two with its Fugaku supercomputer for integrated quantum-classical workflows in a heterogeneous quantum-HPC hybrid computing environment. Fugaku is currently one of the world’s most powerful supercomputers.

QuEra Computing was awarded a ¥6.5 billion (~$41 million) contract by Japan’s National Institute of Advanced Industrial Science and Technology (AIST) to deliver a gate-based neutral-atom quantum computer alongside AIST’s ABCI-Q supercomputer as part of a quantum-classical computing platform.

Novo Holdings, the controlling stakeholder of pharmaceutical company Novo Nordisk, plans to boost the quantum technology startup ecosystem in Denmark with DKK 1.4 billion (~$201 million) in investments.

The University of Sydney received AUD $18.4 million (~$12 million) from the Australian government to help grow the quantum industry and ecosystem.

The European Commission plans to spend €112 million (~$120 million) to support AI and quantum research and innovation.

Research

Intel researchers developed a 300-millimeter cryogenic probing process to collect high-volume data on the performance of silicon spin qubit devices across whole wafers using CMOS manufacturing techniques.

EPFL researchers used a form of ML called deep reinforcement learning (DRL) to train a four-legged robot to avoid falls by switching between walking, trotting, and pronking.=

The University of Cambridge researchers developed tiny, flexible nerve cuff devices that can wrap around individual nerve fibers without damaging them, useful to treat a range of neurological disorders.

Argonne National Laboratory and Toyota are exploring a direct recycling approach that carefully extracts components from spent batteries. Argonne is also working with Talon Metals on a process that could increase the number of EV batteries produced from mined nickel ore.

Events

Find upcoming chip industry events here, including:

Upcoming webinars are here.

Further Reading

Read the latest special reports and top stories, or check out the latest newsletters:

Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials
Automotive, Security and Pervasive Computing

The post Chip Industry Week In Review appeared first on Semiconductor Engineering.

Cadence’s Vatsal Patel stresses the importance of having testing and training capabilities for high-bandwidth memory to prevent the entire SoC from becoming useless and points to key HBM DRAM test instructions through IEEE 1500.

In a podcast, Siemens’ Stephen V. Chavez chats with Anaya Vardya of American Standard Circuits about the growing significance of high density interconnect and Ultra HDI technologies, which enable denser component placement and increased signal integrity compared to traditional PCB designs.

Synopsys’ Ian Land and Randy Fish find that silicon lifecycle management is increasingly being used on chips that target the aerospace and government market to ensure system health and longevity.

Arm’s Hristo Belchev looks at how to enable testing of system designs using the Memory Partitioning and Monitoring (MPAM) Arm architecture supplement, which allows privileged software to partition caches, memory controllers and interconnects on the hardware level.

Keysight’s Jonathon Wright considers where generative AI can add value in software testing by proposing a wide range of scenarios and improving communication between different stakeholders.

Ansys’ Laura Carter checks out how simulation is used to reduce the risks to drivers during a crash in stock car racing.

SEMI’s Maria Daniela Perez chats with Owen J. Guy of Swansea University about the challenge of onboarding talent within the microelectronics industry and the importance of ensuring students receive hands-on experience and exposure to real-world applications.

And don’t miss the blogs featured in the latest Systems & Design newsletter:

Technology Editor Brian Bailey suggests that although it is great to see the DAC conference come back to life, EDA companies need to do something about the show floor.

Siemens’ John Ferguson shows how to glean useful information well before all the details of an assembly are known.

Axiomise’ Ashish Darbari explains how formal verification can help improve chips.

Arteris’ Frank Schirrmeister tracks the race to centralized computing in automotive.

Synopsys’ Andrew Appleby explores the co-optimization of foundation IP and design flows for new transistors.

Cadence’s Anika Sunda looks at controlling the access to physical memory addresses.

Keysight’s Ben Coffin digs into how AI will be used in just about every subsystem of 6G networks.

The post Blog Review: May 1 appeared first on Semiconductor Engineering.

SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how competitive, and potentially lucrative, the HBM market is becoming. SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at the base of the HBM stack.

Intel assembled the industry’s first high-NA EUV lithography system. “Compared to 0.33NA EUV, high-NA EUV (or 0.55NA EUV) can deliver higher imaging contrast for similar features, which enables less light per exposure, thereby reducing the time required to print each layer and increasing wafer output,” Intel said.

Fig. 1: Bigger iron — Intel’s brand new high-NA EUV machinery. Source: Intel

Samsung is slated to receive $6.4 billion in CHIPS ACT funding from the U.S. Department of Commerce (DoC) as part of a $40 billion expansion of its Austin, Texas, manufacturing facility, along with an R&D fab, a pair of leading-edge logic fabs, and an advanced packaging plant in nearby Taylor, Texas.

Micron and the U.S. government next week will announce $6.1 billion in CHIPS Act funding for the development of advanced memory chips in New York and Idaho, according to AP News.

Cadence unveiled its Palladium Z3 Emulation and Protium X3 FPGA Prototyping systems, targeted at multi-billion-gate designs with 2X increase in capacity and a 1.5X performance increase compared to previous-generation systems. Cadence also teamed up with MemVerge to enable seamless support for AWS Spot instances for long-running high-memory EDA jobs, and extended its hybrid cloud environment solutions through a collaboration with NetApp.

Fig. 2: At CadenceLive Silicon Valley, NVIDIA CEO Jensen Huang (r.) discussed accelerated computing and generative AI with Cadence CEO Anirudh Devgan. Source: Semiconductor Engineering

Quick links to more news:

Global
Markets and Money
In-Depth
Security
Education and Workforce
Product and Standards
Research
Quantum
Events
Further Reading

Global

After Taiwan’s recent 7.2 magnitude earthquake, TSMC reached more the 70% tool recovery in its fabs within the first 10 hours and full recovery by the end of the third day, according to this week’s earnings call. Some wafers in process were scrapped but the company expects the lost production to be recovered in the second quarter.  Also in the call, TSMC said they expect their “customers to share some of the higher cost” of the overseas fabs and higher electricity costs.

Advantest‘s regional headquarters in Taiwan donated $2.2 million New Taiwan dollars ($680,000 US) for aid to victims and reconstruction efforts related to the Taiwan earthquake that struck on April 3.

Japan’s exports grew by more than 7% YoY in March, driven by an 11.3% increase in shipments of electronics and semiconductor manufacturing equipment, much of it to China, according to NikkeiAsia.

China‘s IC output grew 40% in the first quarter, primarily driven by EVs and smartphones, according to the South China Morning Post.

In the U.S., the Biden Administration released a notice of funding opportunity of $50 million targeted at small businesses pursuing advances in metrology research and technology. Also, the U.S. Department of Energy announced a $33 million funding opportunity for smart manufacturing technologies.

Germany‘s Fraunhofer IIS launched its On-Board Processor (FOBP) for the German Space Agency’s Heinrich Hertz communication satellite. FOBP can be controlled and reprogrammed from Earth and will be used to investigate creation of hybrid communication networks.

Markets and Money

RISC-V startup Rivos raised more than $250 million in capital investments to tape out its first power-optimized chips for data analytics and generative AI applications.

Silvaco filed to go public on Nasdaq. The company also received a $5 million convertible note investment from Microchip.

Microchip acquired Neuronix AI Labs to provide AI-enabled FPGA solutions for large-scale, high-performance edge applications.

The advanced packaging market saw a modest 4% increase in revenues in Q4 2023 versus the previous quarter, with a projected decline of 13% QoQ in the first quarter of 2024, reports Yole. Overall, the market is expected to increase from $38 billion in 2023 to $69.5 billion in 2029 with a CAGR of 10.7%.

TSMC’s CoWoS total capacity will increase by 150% in 2024 due to demand for NVIDIA’s Blackwell Platform, reports TrendForce.

ASML saw a nearly 40% drop in new litho equipment sales QoQ in Q1 2024 and a 61% drop in net bookings as manufacturers reduced investments in new capital equipment during the recent semiconductor market slump.

Global PC shipments rose about 3% YoY in Q1 2024, and that same growth is expected for full year 2024, reports Counterpoint. Manufacturers are predicted to promote AI PCs as semiconductor companies prepare to launch SoCs featuring higher TOPS.

The GenAI smartphone market share is predicted to reach 11% by 2024 and 43% by 2027, reports Counterpoint. Samsung likely will lead in 2024, but Apple may overtake it in 2025.

The RF GaN market is expected to exceed $2 billion by 2029, fueled by the defense and telecom infrastructure sectors, reports Yole.

In-Depth

Semiconductor Engineering published its Manufacturing, Packaging & Materials newsletter this week. Top articles include:

• Electromigration Concerns Grow In Advanced Packages
• What Works Best For Chiplets
• Enabling Advanced Devices With Atomic Layer Processes

Plus, check out these new stories and tech talks:

• Architecting Chips For High-Performance Computing
• Future-Proofing Automotive V2X
• Secure Movement Of Data In Test
• Challenges With Chiplets and Power Delivery

Security

In security research:

• Seoul National University, Sandia National Laboratories, Texas A&M University, and Applied Materials demonstrated a memristor crossbar architecture for encryption and decryption.
• Robert Bosch, Forschungszentrum Julich, and Newcastle University investigated techniques for error detection and correction in in-memory computing.
• The University of Florida introduced an automated framework that can help identify security assets for a design at the register-transfer level (RTL).

DARPA conducted successful in-air tests of AI flying an F-16 autonomously versus a human-piloted F-16 in visual-range combat scenarios.

The National Security Agency’s Artificial Intelligence Security Center (NSA AISC) published joint guidance on deploying AI systems securely with the Cybersecurity and Infrastructure Security Agency (CISA), the Federal Bureau of Investigation (FBI), and international partners. CISA also issued other alerts.

Products and Standards

Samsung uncorked LPDDR5X DRAM built on a 12nm process that supports up to 10.7 Gbps and expands the single package capacity of mobile DRAM up to 32 GB.

Keysight revealed its next-generation RF circuit simulation tool that supports multi-physics co-design of circuit, electromagnetic, and electrothermal simulations across Cadence, Synopsys, and Keysight platforms.

Renesas released its FemtoClock family of ultra-low jitter clock generators and jitter attenuators with 8 and 12 outputs, enabling clock tree designs for high-speed interconnect systems in telecom and data center switches, routers, medical imaging, and more.

Movellus expanded its droop response solutions with Aeonic Generate AWM3, which responds to voltage droops within 1 to 2 clock cycles while providing enhanced observability for droop profiling and enabling fine-grained dynamic frequency scaling.

Efabless announced the second version of its Python-based open-source EDA software for construction of customizable flows using proprietary or open-source tools.

Faraday Technology licensed Arm’s Cortex-A720AE IP to use in the development of AI-enabled vehicle ASICs. Also, Untether AI teamed up with Arm to enable its inference acceleration technology to be implemented alongside the latest-generation Automotive Enhanced technology from Arm for ADAS and autonomous vehicle applications.

FOXESS used Infineon’s 1,200V CoolSiC MOSFETs and EiceDRIVER gate drivers for industrial energy storage applications, aiming to promote green energy.

Emotors adopted Siemens’ Simcenter solutions for NVH testing of next-gen automotive e-drives.

SiTime debuted a family of clock generators for AI datacenter applications with clock, oscillator, and resonator in an integrated chip.

JEDEC published the JESD79-5C DDR5 SDRAM standard, which includes a DRAM data integrity improvement called Per-Row Activation Counting (PRAC) that precisely counts DRAM activations on a wordline granularity and alerts the system to pause traffic and designate time for mitigation measures when an excessive number of activations are detected.

The LoRa Alliance launched its roadmap for the development of the LoRaWAN open standard for IoT communications, referring to long-range radio (LoRa) low-power wide-area networks (LPWANs).

Education and Workforce

Texas A&M introduced a new Master of Science program for microelectronics and semiconductors, which will begin in fall 2025.

The Cornell NanoScale Science and Technology Facility (CNF) is partnering with Tompkins Cortland Community College and Penn State to offer a free Microelectronics and Nanomanufacturing Certificate Program to veterans and their dependents.

Eindhoven University of Technology (TU/e) has more than 700 researchers and 25 research group focused on the chip industry, but the number is projected to grow significantly due to the Dutch government’s recent investment.

Research

Intel announced a large-scale neuromorphic system based on its Loihi 2 processor. Initially deployed at Sandia National Laboratories, it aims to support research for future brain-inspired AI. Intel is also collaborating with Seekr on next-gen LLM and foundation models.

Los Alamos National Lab, HPE, and NVIDIA collaborated on the design and installation of Venado, the Lab’s new supercomputer. “Venado adds to our cutting-edge supercomputing that advances national security and basic research, and it will accelerate how we integrate artificial intelligence into meeting those challenges,” said Thom Mason, director of Los Alamos National Laboratory in a release.

Penn State is partnering with Morgan Advanced Materials on a five-year, multi-million-dollar research project to advance silicon carbide (SiC) technology. Morgan will become a founding member of the Penn State Silicon Carbide Innovation Alliance. Also, Coherent secured CHIPS Act funding of $15 million for research into high-voltage, high-power silicon carbide and single-crystal diamond semiconductors.

Oak Ridge National Laboratory (ORNL) researchers found a more efficient way to extract lithium from waste liquids leached from mining sites, oil fields, and used batteries.

Quantum

Quantinuum said it reached an inherent 99.9% 2-qubit gate fidelity in its commercial quantum computer, a point at which quantum error correction protocols can be used to greatly reduce error rates.

D-Wave Quantum uncorked a fast-anneal feature to speed up computations on its quantum processing units, which reduces the impact of external disturbances.

MIT researchers outlined a new conceptual model for a quantum computer that aims to make writing code for them easier.

SLAC National Accelerator Laboratory, Stanford University, Max Planck Institute of Quantum Optics, Ludwig-Maximilians-Universitat Munich, and Instituto de Ciencia de Materiales de Madrid researchers proposed a method that harnesses the structure of light to tweak the properties of quantum materials.

Events

Find upcoming chip industry events here, including:

Upcoming webinars are here.

Further Reading

Read the latest special reports and top stories, or check out the latest newsletters:

Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials
Automotive, Security and Pervasive Computing

The post Chip Industry Week In Review appeared first on Semiconductor Engineering.

SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how competitive, and potentially lucrative, the HBM market is becoming. SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at the base of the HBM stack.

Intel assembled the industry’s first high-NA EUV lithography system. “Compared to 0.33NA EUV, high-NA EUV (or 0.55NA EUV) can deliver higher imaging contrast for similar features, which enables less light per exposure, thereby reducing the time required to print each layer and increasing wafer output,” Intel said.

Fig. 1: Bigger iron — Intel’s brand new high-NA EUV machinery. Source: Intel

Samsung is slated to receive $6.4 billion in CHIPS ACT funding from the U.S. Department of Commerce (DoC) as part of a $40 billion expansion of its Austin, Texas, manufacturing facility, along with an R&D fab, a pair of leading-edge logic fabs, and an advanced packaging plant in nearby Taylor, Texas.

Micron and the U.S. government next week will announce $6.1 billion in CHIPS Act funding for the development of advanced memory chips in New York and Idaho, according to AP News.

Cadence unveiled its Palladium Z3 Emulation and Protium X3 FPGA Prototyping systems, targeted at multi-billion-gate designs with 2X increase in capacity and a 1.5X performance increase compared to previous-generation systems. Cadence also teamed up with MemVerge to enable seamless support for AWS Spot instances for long-running high-memory EDA jobs, and extended its hybrid cloud environment solutions through a collaboration with NetApp.

Fig. 2: At CadenceLive Silicon Valley, NVIDIA CEO Jensen Huang (r.) discussed accelerated computing and generative AI with Cadence CEO Anirudh Devgan. Source: Semiconductor Engineering

Quick links to more news:

Global
Markets and Money
In-Depth
Security
Education and Workforce
Product and Standards
Research
Quantum
Events
Further Reading

Global

After Taiwan’s recent 7.2 magnitude earthquake, TSMC reached more the 70% tool recovery in its fabs within the first 10 hours and full recovery by the end of the third day, according to this week’s earnings call. Some wafers in process were scrapped but the company expects the lost production to be recovered in the second quarter.  Also in the call, TSMC said they expect their “customers to share some of the higher cost” of the overseas fabs and higher electricity costs.

Advantest‘s regional headquarters in Taiwan donated $2.2 million New Taiwan dollars ($680,000 US) for aid to victims and reconstruction efforts related to the Taiwan earthquake that struck on April 3.

Japan’s exports grew by more than 7% YoY in March, driven by an 11.3% increase in shipments of electronics and semiconductor manufacturing equipment, much of it to China, according to NikkeiAsia.

China‘s IC output grew 40% in the first quarter, primarily driven by EVs and smartphones, according to the South China Morning Post.

In the U.S., the Biden Administration released a notice of funding opportunity of $50 million targeted at small businesses pursuing advances in metrology research and technology. Also, the U.S. Department of Energy announced a $33 million funding opportunity for smart manufacturing technologies.

Germany‘s Fraunhofer IIS launched its On-Board Processor (FOBP) for the German Space Agency’s Heinrich Hertz communication satellite. FOBP can be controlled and reprogrammed from Earth and will be used to investigate creation of hybrid communication networks.

Markets and Money

RISC-V startup Rivos raised more than $250 million in capital investments to tape out its first power-optimized chips for data analytics and generative AI applications.

Silvaco filed to go public on Nasdaq. The company also received a $5 million convertible note investment from Microchip.

Microchip acquired Neuronix AI Labs to provide AI-enabled FPGA solutions for large-scale, high-performance edge applications.

The advanced packaging market saw a modest 4% increase in revenues in Q4 2023 versus the previous quarter, with a projected decline of 13% QoQ in the first quarter of 2024, reports Yole. Overall, the market is expected to increase from $38 billion in 2023 to $69.5 billion in 2029 with a CAGR of 10.7%.

TSMC’s CoWoS total capacity will increase by 150% in 2024 due to demand for NVIDIA’s Blackwell Platform, reports TrendForce.

ASML saw a nearly 40% drop in new litho equipment sales QoQ in Q1 2024 and a 61% drop in net bookings as manufacturers reduced investments in new capital equipment during the recent semiconductor market slump.

Global PC shipments rose about 3% YoY in Q1 2024, and that same growth is expected for full year 2024, reports Counterpoint. Manufacturers are predicted to promote AI PCs as semiconductor companies prepare to launch SoCs featuring higher TOPS.

The GenAI smartphone market share is predicted to reach 11% by 2024 and 43% by 2027, reports Counterpoint. Samsung likely will lead in 2024, but Apple may overtake it in 2025.

The RF GaN market is expected to exceed $2 billion by 2029, fueled by the defense and telecom infrastructure sectors, reports Yole.

In-Depth

Semiconductor Engineering published its Manufacturing, Packaging & Materials newsletter this week. Top articles include:

• Electromigration Concerns Grow In Advanced Packages
• What Works Best For Chiplets
• Enabling Advanced Devices With Atomic Layer Processes

Plus, check out these new stories and tech talks:

• Architecting Chips For High-Performance Computing
• Future-Proofing Automotive V2X
• Secure Movement Of Data In Test
• Challenges With Chiplets and Power Delivery

Security

In security research:

• Seoul National University, Sandia National Laboratories, Texas A&M University, and Applied Materials demonstrated a memristor crossbar architecture for encryption and decryption.
• Robert Bosch, Forschungszentrum Julich, and Newcastle University investigated techniques for error detection and correction in in-memory computing.
• The University of Florida introduced an automated framework that can help identify security assets for a design at the register-transfer level (RTL).

DARPA conducted successful in-air tests of AI flying an F-16 autonomously versus a human-piloted F-16 in visual-range combat scenarios.

The National Security Agency’s Artificial Intelligence Security Center (NSA AISC) published joint guidance on deploying AI systems securely with the Cybersecurity and Infrastructure Security Agency (CISA), the Federal Bureau of Investigation (FBI), and international partners. CISA also issued other alerts.

Products and Standards

Samsung uncorked LPDDR5X DRAM built on a 12nm process that supports up to 10.7 Gbps and expands the single package capacity of mobile DRAM up to 32 GB.

Keysight revealed its next-generation RF circuit simulation tool that supports multi-physics co-design of circuit, electromagnetic, and electrothermal simulations across Cadence, Synopsys, and Keysight platforms.

Renesas released its FemtoClock family of ultra-low jitter clock generators and jitter attenuators with 8 and 12 outputs, enabling clock tree designs for high-speed interconnect systems in telecom and data center switches, routers, medical imaging, and more.

Movellus expanded its droop response solutions with Aeonic Generate AWM3, which responds to voltage droops within 1 to 2 clock cycles while providing enhanced observability for droop profiling and enabling fine-grained dynamic frequency scaling.

Efabless announced the second version of its Python-based open-source EDA software for construction of customizable flows using proprietary or open-source tools.

Faraday Technology licensed Arm’s Cortex-A720AE IP to use in the development of AI-enabled vehicle ASICs. Also, Untether AI teamed up with Arm to enable its inference acceleration technology to be implemented alongside the latest-generation Automotive Enhanced technology from Arm for ADAS and autonomous vehicle applications.

FOXESS used Infineon’s 1,200V CoolSiC MOSFETs and EiceDRIVER gate drivers for industrial energy storage applications, aiming to promote green energy.

Emotors adopted Siemens’ Simcenter solutions for NVH testing of next-gen automotive e-drives.

SiTime debuted a family of clock generators for AI datacenter applications with clock, oscillator, and resonator in an integrated chip.

JEDEC published the JESD79-5C DDR5 SDRAM standard, which includes a DRAM data integrity improvement called Per-Row Activation Counting (PRAC) that precisely counts DRAM activations on a wordline granularity and alerts the system to pause traffic and designate time for mitigation measures when an excessive number of activations are detected.

The LoRa Alliance launched its roadmap for the development of the LoRaWAN open standard for IoT communications, referring to long-range radio (LoRa) low-power wide-area networks (LPWANs).

Education and Workforce

Texas A&M introduced a new Master of Science program for microelectronics and semiconductors, which will begin in fall 2025.

The Cornell NanoScale Science and Technology Facility (CNF) is partnering with Tompkins Cortland Community College and Penn State to offer a free Microelectronics and Nanomanufacturing Certificate Program to veterans and their dependents.

Eindhoven University of Technology (TU/e) has more than 700 researchers and 25 research group focused on the chip industry, but the number is projected to grow significantly due to the Dutch government’s recent investment.

Research

Intel announced a large-scale neuromorphic system based on its Loihi 2 processor. Initially deployed at Sandia National Laboratories, it aims to support research for future brain-inspired AI. Intel is also collaborating with Seekr on next-gen LLM and foundation models.

Los Alamos National Lab, HPE, and NVIDIA collaborated on the design and installation of Venado, the Lab’s new supercomputer. “Venado adds to our cutting-edge supercomputing that advances national security and basic research, and it will accelerate how we integrate artificial intelligence into meeting those challenges,” said Thom Mason, director of Los Alamos National Laboratory in a release.

Penn State is partnering with Morgan Advanced Materials on a five-year, multi-million-dollar research project to advance silicon carbide (SiC) technology. Morgan will become a founding member of the Penn State Silicon Carbide Innovation Alliance. Also, Coherent secured CHIPS Act funding of $15 million for research into high-voltage, high-power silicon carbide and single-crystal diamond semiconductors.

Oak Ridge National Laboratory (ORNL) researchers found a more efficient way to extract lithium from waste liquids leached from mining sites, oil fields, and used batteries.

Quantum

Quantinuum said it reached an inherent 99.9% 2-qubit gate fidelity in its commercial quantum computer, a point at which quantum error correction protocols can be used to greatly reduce error rates.

D-Wave Quantum uncorked a fast-anneal feature to speed up computations on its quantum processing units, which reduces the impact of external disturbances.

MIT researchers outlined a new conceptual model for a quantum computer that aims to make writing code for them easier.

SLAC National Accelerator Laboratory, Stanford University, Max Planck Institute of Quantum Optics, Ludwig-Maximilians-Universitat Munich, and Instituto de Ciencia de Materiales de Madrid researchers proposed a method that harnesses the structure of light to tweak the properties of quantum materials.

Events

Find upcoming chip industry events here, including:

Upcoming webinars are here.

Further Reading

Read the latest special reports and top stories, or check out the latest newsletters:

Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials
Automotive, Security and Pervasive Computing

The post Chip Industry Week In Review appeared first on Semiconductor Engineering.

By Adam Kovac, Gregory Haley, and Liz Allan.

Cadence plans to acquire BETA CAE Systems for $1.24 billion, the latest volley in a race to sell multi-physics simulation and analysis across a broad set of customers with deep pockets. Cadence said the deal opens the door to structural analysis for the automotive, aerospace, industrial, and health care sectors. Under the terms of the agreement, 60% of the purchase would be paid in cash, and the remainder in stock.

South Korea’s National Intelligence Service reported that North Korea was targeting cyberattacks at domestic semiconductor equipment companies, using a “living off the land” approach, in which the attacker uses minimal malware to attack common applications installed on the server. That makes it more difficult to spot an attack. According to the government, “In December last year, Company A, and in February this year, Company B, had their configuration management server and security policy server hacked, respectively, and product design drawings and facility site photos were stolen.”

As the memory market goes, so goes the broader chip industry. Last quarter, and heading into early 2024, both markets began showing signs of sustainable growth. DRAM revenue jumped 29.6% in Q4 for a total of $17.46 billion. TrendForce attributed some of that to  new efforts to stockpile chips and strategic production control. NAND flash revenue was up 24.5% in Q4, with solid growth expected to continue into the first part of this year, according to TrendForce. Revenue for the sector topped $11.4 billion in Q4, and it’s expected to grow another 20% this quarter. SSD prices rebounded in Q4, as well, up 15% to $23.1 billion. Across the chip industry, sales grew 15.2% in January compared to the same period in 2023, according to the Semiconductor Industry Association (SIA). This is the largest increase since May 2022, and that trend is expected to continue throughout 2024 with double-digit growth compared to 2023.

Marvell said it is working with TSMC to develop a technology platform for the rapid deployment of analog, mixed-signal, and foundational IP. The company plans to sell both custom and commercial chiplets at 2nm.

The Dutch government is concerned that ASML, the only maker of EUV/high-NA EUV lithography equipment in the world, is considering leaving the Netherlands, according to De Telegraaf.

Quick links to more news:

Design and Power
Manufacturing and Test
Automotive and Batteries
Security
Pervasive Computing and AI
Events

Design and Power

AMD appears to have hit a roadblock with the U.S. Department of Commerce (DoC) over a new AI chip it designed for the Chinese market, as reported by Bloomberg. U.S. officials told the company the new chip is too powerful to be sold without a license.

JEDEC released its new memory standard as a free download on its website. The JESD239 Graphics Double Data Rate SGRAM can reach speeds of 192 GB/s and improve signal-to-noise ratio.

Accellera rolled out its IEEE Std. 1800‑2023 Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language, which is now available for free download. The decision to offer it at no cost is due to Accellera’s participation in the IEEE GET Program, which was founded in 2010 with the intention of providing  open access to some standards. Accellera also announced it had approved for release the Verilog-AMS 2023 standard, which offers enhancements to analog constructs, dynamic tolerance for event control statements, and other upgrades.

Chiplets are a hot topic these days. Six industry experts discuss chiplet standards, interoperability, and the need for highly customized AI chiplets.

Optimizing EDA hardware for the cloud can shorten the time required for large and complex simulations, but not all workloads will benefit equally, and much more can be done to improve those that can.

Flex Logix is developing InferX DSP for use with existing EFLX eFPGA from 40nm to 7nm. InferX achieves about 30 times the DSP performance/mm² than eFPGA.

The number of challenges is growing in power semiconductors, just as it is in traditional chips. This tech talk looks at integrating power semiconductors with other devices, different packaging impacts, and how these devices will degrade over time.

Vultr announced it will use NVIDIA’s HGX H100 GPU clusters to expand its Seattle-based cloud data center. The company said the expansion, which will be powered by hydroelectricity, will make the facility one of the cleanest, most power efficient data centers in the country.

Amazon Web Services will expand its presence in Saudi Arabia, announcing a new $5.3 billion infrastructure region in the country that will launch in 2026. The new region will offer developers, entrepreneurs and companies access to healthcare, education and other services.

Google is teaming up with the Geneva Science and Diplomacy Anticipator (GESDA) to launch the XPRIZE Quantum Applications, with a $5 million in prizes for winners who can demonstrate ways to use quantum computing to solve real-world problems. Teams must submit a proposal that includes analysis of how long their algorithm would need to run before reaching a solution to a problem, such as improving drug development or designing new battery materials.

South Korea’s nepes corporation has turned to Siemens EDA for solutions in the development of advanced 3D-IC packages. The deal will see nepes incorporating several Siemens technologies, including the Calibre nmPlatform, Hyperlynx software and Xpedition Substrate Integrator software.

Siemens also formalized a partnership with Nuclei System Technology in which the pair of companies will work together on solution support for Nuclei’s RISC-V processor cores. The collaboration will allow clients to monitor CPU program execution in real-time via Nuclei’s RISC-V CPU Ips.

Keysight and ETS-Lindgren announced a breakthrough test solution for cellular devices using non-terrestrial networks. The solution is capable of measuring and validating the performance of both the transmitter and receiver of devices capable of supporting the network.

Nearly fifty companies raised $800 million for power electronics, data center interconnects, and more last month.

Manufacturing and Test

SEMI Europe issued a position statement to the European Union, warning against additional export controls or rules on foreign investment. SEMI argued that free trade partnerships are a better method for ensuring security than bans or restrictions.

Revenues for the top five wafer fab equipment manufacturers declined 1% YoY in 2023 to $93.5 billion, according to Counterpoint Research. The drop was attributed to weak spending on memory, inventory adjustments, and low demand in consumer electronics. The tide is changing, though.

Bruker closed two acquisitions. One involved Chemspeed Technologies, a Switzerland-based provider of automated laboratory R&D and QC workflow solutions. The second involved Phasefocus, an image processing company based in the UK.

A Swedish company, SCALINQ, released a commercially available large-scale packaging solution capable of controlling quantum devices with hundreds of qubits.

Solid Sands, a provider of testing and qualification technology for compilers and libraries, will partner with California-based Emprog to establish a representative presence in the U.S.

Automotive

Tesla halted production at its Brandenberg, Germany, gigafactory after an environmental activist group attacked an electricity pylon, reports the Guardian.

Stellantis will invest €5.6 billion (~$6.1B) in South America to support more than 40 new products, decarbonization technologies, and business opportunities.

The amount of data being collected, processed, and stored in vehicles is exploding, and so is the value of that data. That raises questions that are still not fully answered about how that data will be used, by whom, and how it will be secured.

While industry experts expect many benefits of V2X technology, technological and social hurdles to cross. But there is progress.

Infineon released its next-gen silicon carbide (SiC) MOSFET trench technology with 650V and 1,200V options improving stored energies and charges by up to 20%, ideal for power semiconductor applications such as photovoltaics, energy storage, DC EV charging, motor drives, and industrial power supplies.

Hyundai selected Ansys to supply structural simulation solutions for vehicle body system analysis, providing end-to-end, predictively accurate capabilities for virtual performance validation.

ION Mobility used the Siemens Xcelerator portfolio for styling, mechanical engineering, and electric battery pack development for its ION M1-S electric motorbike.

Ethernovia sampled a family of automotive PHY transceivers that scale from 10 Gbps to 1 Gbps over 15 meters of automotive cabling.

The California Public Utilities Commission (CPUC) approved Waymo’s plan to expand its driverless robotaxi services to Los Angeles and other cities near San Francisco, reports Reuters.

By 2027, next-gen battery EVs (BEVs) will on average be cheaper to produce than comparable gas-powered cars, reports Gartner. But the firm noted that average cost of EV accident repair will rise by 30%, and 15% of EV companies founded in the last decade will be acquired or bankrupt.

University of California San Diego (UCSD) researchers developed a cathode material for solid-state lithium-sulfur batteries that is electrically conductive and structurally healable.

ION Storage Systems announced its anodeless and compressionless solid-state batteries (SSBs) achieved 125 cycles with under 5% capacity degradation in performance. ION has been working with the U.S. Department of Defense (DoD) to test its SSB before expanding into markets such as EVs, energy storage, consumer electronics, and aerospace.

Security

Advanced process nodes and higher silicon densities are heightening DRAM’s susceptibility to Rowhammer attacks, as reduced cell spacing significantly decreases the hammer count needed for bit flips. A multi-layered, system-level approach is crucial to DRAM protection.

Researchers at Bar-Ilan University and Rafael Defense Systems proposed an analytical electromagnetic model for IC shielding against hardware attacks.

Keysight acquired the IP of Firmalyzer, whose firmware security analysis technology will be integrated into the Keysight IoT Security Assessment and Automotive Security solutions, providing analysis into what is happening inside the IoT device itself.

Flex Logix joined the Intel Foundry U.S. Military Aerospace Government (USMAG) Alliance, ensuring U.S. defense industrial base and government customers have access to the latest technology, enabling successful designs for mission critical programs.

The EU Council presidency and European Parliament reached a provisional agreement on a Cyber Solidarity Act and an amendment to the Cybersecurity Act (CSA) concerning managed security services.

The EU Agency for Cybersecurity (ENISA) and partners updated the compendium on elections cybersecurity in response to issues such as AI deep fakes, hacktivists-for-hire, the sophistication of threat actors, and the current geopolitical context.

The Cybersecurity and Infrastructure Security Agency (CISA) launched efforts to help secure the open source software ecosystem; updated its Public Safety Communications and Cyber Resiliency Toolkit; and issued other alerts including security advisories for VMware, Apple, and Cisco.

Pervasive Computing and AI

Johns Hopkins University engineers used natural language prompts and ChatGPT4 to produce detailed instructions to build a spiking neural network (SNN) chip. The neuromorphic accelerators could power real-time machine intelligence for next-gen embodied systems like autonomous vehicles and robots.

The global AI hardware market size was estimated at $53.71 billion in 2023, and is expected to reach about $473.53 billion by 2033, at a compound annual growth rate of 24.5%, reports Precedence Research.

National Institute of Standards and Technology (NIST) researchers and partners built compact chips capable of converting light into microwaves, which could improve navigation, communication, and radar systems.

Fig. 1: NIST researchers test a chip for converting light into microwave signals. Pictured is the chip, which is the fluorescent panel that looks like two tiny vinyl records. The gold box to the left of the chip is the semiconductor laser that emits light to the chip. Credit: K. Palubicki/NIST

The Indian government is investing 103 billion rupees ($1.25B) in AI projects, including computing infrastructure and large language models (LLMs).

Infineon is collaborating with Qt Group, bringing Qt’s graphics framework to Infineon’s graphics-enabled TRAVEO T2G cluster MCUs to optimize graphical user interface (GUI) development.

Keysight leveraged fourth-generation AMD EPYC CPUs to develop a new benchmarking methodology to test mobile and 5G private network performance. The method uses realistic traffic generation to uncover a CPU’s true power and scalability while observing bandwidth requirements.

The AI industry is pushing a nuclear power revival, reports NBC, and Amazon bought a nuclear-powered data center in Pennsylvania from Talen Energy for $650 million, according to WNEP.

Bank of America was awarded 644 patents in 2023 for technology including information security, AI, machine learning (ML), online and mobile banking, payments, data analytics, and augmented and virtual reality (AR/VR).

Mistral AI’s large language model, Mistral Large, became available in the Snowflake Data Cloud for customers to securely harness generative AI with their enterprise data.

China’s smartphone unit sales declined 7% year over year in the first six weeks of 2024, with Apple declining 24%, reports Counterpoint.

Shipments of LCD TV panels are expected to reach 55.8 million units in Q1 2024, a 5.3% quarter over quarter increase, reports TrendForce. And an estimated 5.8 billion LED lamps and luminaires are expected to reach the end of their lifespan in 2024, triggering a wave of secondary replacements and boosting total LED lighting demand to 13.4 billion units.

Korea Institute of Science and Technology (KIST) researchers mined high-purity gold from electrical and electronic waste.

The San Diego Supercomputer Center (SDSC) and the University of Utah launched a National Data Platform pilot project, aimed at making access to and use of scientific data open and equitable.

Events

Find upcoming chip industry events here, including:

Upcoming webinars are here.

Further Reading and Newsletters

Read the latest special reports and top stories, or check out the latest newsletters:

Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials
Automotive, Security and Pervasive Computing

The post Chip Industry Week In Review appeared first on Semiconductor Engineering.

The amount of data being collected, processed, and stored in vehicles is exploding, and so is the value of that data. That raises questions that are still not fully answered about how that data will be used, by whom, and how it will be secured.

Automakers are competing based on the latest versions of advanced technologies such as ADAS, 5G, and V2X, but the ECUs, software-defined vehicles, and in-cabin monitoring also demand more and more data, and they are using that data for purposes that extend beyond just getting the vehicle from point A to point B safely. They now are vying to offer additional subscription-based services according to customers’ interests, as various entities, including insurance companies, indicate a willingness to pay for information on drivers’ habits.

Collecting this data can help OEMs gain insights and potentially generate additional revenue. However, gathering it raises privacy and security concerns about who will own this massive amount of data and how it should be managed and used. And as automotive data use increases, how will it impact future automotive design?

Fig. 1: Connected vehicles rely on software to communicate between vehicles and the cloud. Source: McKinsey & Co.

“Much of the data generated in the vehicle will have immense value to OEMs and their partners for analyzing driver behavior and vehicle performance and for developing new or enhanced features,” said Sven Kopacz, autonomous vehicle section manager at Keysight Technologies. “On the other hand, the privacy of data use can be viewed as a risk to some. But the real value – as already implemented and used by Tesla and others – is the constant feedback to improve those ADAS algorithms, enable a CI/CD DevOps software development model, and allow the rapid download of updates. Only time will tell if law enforcement and the courts will demand this data and how lawmakers will respond.”

Types of data generated
According to Precedence Research, the global automotive data market size will grow from $2.19 billion in 2022 to $14.29 billion by 2032, with many types of data collected, including:

• Autonomous driving: Data on all levels, from L1 to L5, including that collected from the multiple sensors installed on vehicles.
• Infrastructure: Remote monitoring, OTA updates, and data used for remote control by control centers, V2X, and traffic patterns.
• Infotainment: Information on how customers are using applications, such as voice control, gesture, maps, and parking.
• Connected information: Information on payment to third-party parking apps, accident information, data from dashboard cameras, handheld devices, mobile applications, and driver behavior monitoring.
• Vehicle health: Repair and maintenance records, insurance underwriting, fuel consumption, telematics.

This information may be useful for future automotive design, predictive maintenance, and safety improvements, and insurance companies are expected to be able to reduce underwriting costs with more comprehensive information on accidents. Based on the information collected, OEMs should be able to design more reliable and safer cars, and to stay in close touch with customer wants. For example, experiments can be conducted to gauge customer demand for subscription-based services such as automatic parking and more sophisticated voice input and commands.

“Diagnostic data for service and repair has been a core of automotive data analytics for decades,” noted Lorin Kennedy, senior staff product management manager for SLM in-field analytics at Synopsys. “With the advent of connected vehicles and advanced machine learning (ML) analytics, which enable a greater quantity of data to be routinely processed, this data has gained exponentially in value. As data drives feature enhancements such as mobile-like experiences and advanced driver assist capabilities, OEMs increasingly need to better understand the dependability and reliability of the semiconductor systems powering these new features. The collection of monitoring and sensor data from electronic components and the semiconductors themselves will be a growing diagnostic data requirement across all types of automotive technologies like ADAS, IVI, ECUs, etc. to ensure quality and reliability on these more advanced nodes.”

Anticipated updates to ISO 26262 regulations regarding the application of predictive maintenance to hardware, identifying degrading intermittent faults caused by silicon aging, and over-stress conditions in the field are areas to be addressed, as well. Those can include silicon lifecycle management (SLM) technologies, which can deliver more comprehensive knowledge about the health and remaining useful life of silicon as it ages.

“That knowledge, in turn, will enable service updates and future OTA releases that leverage additional semiconductor compute power,” Kennedy said. “Overall fleet performance will benefit, and the semiconductor and system design process will, too, as new insights help achieve greater efficiencies. OEM, Tier One, and semiconductor supplier collaboration on what the data brings to light – from silicon to software system performance – will enable vehicles to meet the functional safety design parameters that are becoming increasingly crucial in advanced electronics.”

Still, for data generated in vehicles, OEMs will need to prioritize which data can provide value for drivers immediately, and which data should be sent to the cloud via 5G connections.

“Tradeoffs between on-board processing to reduce data volume and data transmission network costs will likely dictate prioritization,” Keysight’s Kopacz said. “For example, camera, lidar, and radar sensor data for ADAS applications may have value for training ADAS algorithms, but the volume of raw data will be very costly to transmit and store. Likewise, driver attention data can have high value in UI design, and would be best gathered in a meta-data form. V2X data has a relatively lower data volume and should ultimately be a key data source for ADAS, providing in-car non-line-of-sight visibility of other vehicles, road infrastructure, and road conditions. Sharing this over V2N links can enable effective safety applications, but angle random walk (ARW) sensor data needs to be considered more carefully due to its complex nature. Infotainment streaming content into the vehicle also can be a valuable revenue stream for OEMs, and the content providers as well, as network operators working together.”

Impacts on automotive cybersecurity
As vehicles become more autonomous and connected, data use will increase, and so will the value of that data. This raises cybersecurity and data privacy concerns. Hackers want to steal personal data collected by the vehicles, and can use ransomware and other attacks to do so. The idea of taking control of vehicles — or worse, stealing them — also attracts hackers. Techniques used include hacking vehicle apps and wireless connections on the vehicles (diagnostics, key fob attacks and keyless jamming). Protecting data access, vehicles, and infrastructure from attacks is increasingly important and challenging.

Cybersecurity risks increase with software-defined vehicles. Memory especially will need to be safeguarded.

“The integration of advanced technology into EVs poses significant cybersecurity challenges that demand immediate attention and sophisticated solutions,” said Ilia Stolov, center head of secure memory solution at Winbond. “Central to the digital fortresses within modern electronic platforms are flash non-volatile memories, housing invaluable assets like code, private data, and company credentials. Unfortunately, their ubiquity has rendered them attractive targets for hackers seeking unauthorized access to sensitive information.”

Stolov noted that Winbond has been actively working to secure flash memory from hacks.

Additionally, there are important considerations in securing memory designs, such as:

• DICE root of trust: The Device Identifier Composition Engine (DICE) should be used to create the secure flash root of trust for hardware security. This secure identity forms the basis for building trust in the hardware. Other security measures can therefore rely on the authenticity and integrity of the boot code, protecting against firmware and software attacks. The initial boot process and subsequent software execution are based on trusted and verified measurements, helping prevent the injection of malicious code into the system.
• Code and data protection: Protecting code and data is crucial for maintaining system-wide integrity. Unauthorized modifications to code or data can lead to malfunctions, system instability, or the introduction of malicious code, compromising the hardware’s intended functionality or exploiting system vulnerabilities.
• Authentication protocols: Authentication is a fundamental and crucial component of cybersecurity, serving as the frontline defense against unauthorized access and potential security breaches. Employing authentication protocols to restrict access to authorized actors and approved software layers only using cryptography credentials is important.
• Secure software updates with rollback protection: Regular updates extend beyond bug fixes including remote firmware over-the-air (OTA) updates, guards against rollback attacks, and ensures the execution of only legitimate updates.
• Post-quantum cryptography: Anticipating the post-quantum computing era to include NIST 800-208 Leighton-Micali Signature (LMS) cryptography safeguards EVs against the potential threats posed by future quantum computers.
• Platform resiliency: Automatic detection of unauthorized code changes enables swift recovery to a secure state, effectively thwarting potential cyber threats. Adhering to NIST 800-193 recommendations for platform resiliency ensures a robust defense mechanism.
• Secure supply chain: Guaranteeing the origin and integrity of flash content throughout the supply chain, these secure flash devices prevent content tampering and misconfiguration during platform assembly, transportation, and configuration. This, in turn, safeguards against cyber adversaries.

Considering the transition to SDVs and connected cars, data vulnerability becomes even more significant.

“Depending on where data resides, different protection measures are in place,” said Keysight’s Kopacz. “Intrusion detection systems (IDS), crypto services, and key management are becoming standard solutions in vehicles. Especially sensitive data for safety features needs to be protected and verified. Thus, redundancy becomes more relevant. With SDVs, the vehicle software is constantly updated or changed throughout the entire vehicle life cycle. Ever-evolving cyber threats are particularly challenging. Accordingly, the entire vehicle software must be continuously checked for new security gaps. OEMs are going to need comprehensive testing solutions to minimize security threats. This will need to include the cybersecurity testing of the entire attack surface, covering all vehicle interfaces – wired vehicle communication networks such as CAN or automotive Ethernet or wireless connections via Wi-Fi, Bluetooth, or cellular communications. OEMs will also need to test the backend that provides over-the-air (OTA) software updates. Such solutions can reduce the risk of damage or data theft by cybercriminals.”

Data management and privacy concerns
Another issue to be resolved is how the massive amount of data collected will be managed and used. Ideally, data will be analyzed to yield commercial value without causing privacy concerns. For example, infotainment platform data might reveal what types of music are most popular, helping the music industry to improve marketing strategies. Who will monitor the transfer of such data, though? How will customers be made aware of the data collection? And will they have an opportunity to opt out of having their data sold?

As with airplanes, vehicle black boxes are installed to record information for analysis of the data after an accident occurs. The information recorded includes vehicle speed, the braking situation, and the activation of air bags, among other things. If an accident occurs resulting in a fatality, and the data from ADAS and ECU uncover vulnerability in the designs, could that data be used as evidence in court against manufacturers or their supply chains? Armed with this information, the insurance industry may decline claims. Would one or more manufacturers of the ADAS/ECU be required to hand over the data when ordered by the authorities?

“Quality requirements for sophisticated electronic parts will continue to become more rigid and strict, allowing only a few defective parts per billion (DPPB) due to the impact failed components can have on the safety and well-being of human life,” noted Guy Cortez, senior staff product management manager for SLM analytics at Synopsys. “SLM data analytics will continue to play a substantial role in the health, maintainability, and sustainability of these devices throughout their life within the vehicle. Through the power of analytics, you can do proper root cause analysis of any failed device (e.g., return merchandise authorization, or RMA). What’s more, you will also be able to find ‘like’ devices that ultimately may exhibit similar failed behavior over time. Thus empowered, you can proactively recall these like devices before they fail during operation in the field. Upon further analysis, the device(s) in question may require a design re-spin by the device developer in order to correct any identified issue. With a proper SLM solution deployed throughout the automotive ecosystem, you can achieve a higher level of predictability, and thus higher quality and safety for the automotive manufacturer and consumer.”

OEM impact
While modern cars have been described as computers on wheels, they are now more like mobile phones on wheels. OEMs are designing cars that do not skimp on features. Semi-autonomous driving, voice-controlled infotainment systems, and the monitoring of many functions—including driver behavior— are yielding a large amount of data. While that data can be used to improve future designs. OEMs’ approaches to security and privacy vary, with some offering stronger security and privacy protection than others.

Mercedes-Benz is paying attention to data security and privacy, and is compliant to UN ECE R155 / R156, a European norm for cybersecurity and software update management systems, according to the company. Which data is processed in connection with digital vehicle services depends on which services the customer selects. Only the data required for the respective service will be processed. Additionally, the “Mercedes me connect” app’s terms of use and privacy information make it transparent for customers to see what data is needed for and how it is processed. Customers can determine which services they want to use.

Hyundai indicated it would follow a user-centric focus, prioritizing safety, information security, and data privacy with fault-tolerant software architectures to enhance cybersecurity. Hyundai Motor Group’s global software center, 42dot, is currently developing integrated hardware/software security solutions that detect and block data tampering, hacking, and external cyber threats, as well as abnormal communication using big data and AI algorithms.

And according to the BMW Group, the company manages a connected fleet of more than 20 million vehicles globally. More than 6 million vehicles are updated over-the-air on a regular basis. Together with other services, more than 110 terabytes of data traffic per day are processed between the connected vehicles and cloud-backend. All BMW vehicle interfaces permit consumers to opt in or out of various types of data collection and processing that may happen on their vehicles. If preferred, BMW customers may opt out of all optional data collection relating to their vehicles at any time by visiting the BMW iDrive screen in their vehicle. Additionally, to completely stop the transfer of any data from BMW vehicles to BMW services, customers can contact the company to request that the embedded SIM on their vehicles be disabled.

Not all OEMs hold the same philosophy on privacy. According to a study on 25 brands conducted by the Mozilla Foundation, a nonprofit organization, 56% will share data with law enforcement in response to an informal request, 84% share or sell personal data, and 100% earned the foundation’s “privacy not included” warning label.

More importantly, are customers educated or informed on the privacy issue?

Fig. 2: Once data is collected from a vehicle, it can go to multiple destinations without the knowledge of customers. Source: Mozilla, *Privacy Not Included.

Applying data to automotive design in the future
OEMs collect many different types of automotive data in relation to autonomous driving, infrastructure, infotainment, connected vehicles, and vehicle health and maintenance. The ultimate goal, however, is not just to compile massive raw data; rather, it is to extract value from it. One of the questions OEMs need to ask is how to apply technology to extract information that is really useful in future automotive design.

“OEMs are trying to test and validate the various functions of their vehicles,” said David Fritz, vice president of virtual and hybrid systems at Siemens EDA. “This can involve millions of terabytes of data. Sometimes, a huge portion of the data is redundant and useless. The real value in the data is, once it gets distilled, that it’s in a form where humans can relate to the meaning of the data, and it also can be pushed into the systems while they’re being developed and tested and before the vehicles are even on the ground. We’ve known for quite some time that many countries and regulatory bodies around the world have been collecting what they call an accident database. When an accident occurs, the police show up on the scene collecting relevant data. ‘There was an intersection here, a stop sign there. And this car was traveling in this direction roughly this many miles an hour. The weather condition is this. The car entered the intersection in the yellow light and caused an accident, etc.’ This is an accident scenario. Technologies are available to take those scenarios and put them in a standard form called Open Scenario. Based on the information, a new set of data can be generated to determine what the sensors would be seeing in those accident situations, and then push it through both a virtual version of the vehicle and environment and in the future, and push those scenarios through the sensors in this physical vehicle itself. This is really the distillation of that data into a form that a human can wrap their mind around. Otherwise, you could collect billions of terabytes of raw data and try to push that into these systems, and it wouldn’t actually help you any more than if someone were sitting in a car and dragging those for billions of miles.”

But that data also can be very useful. “If an OEM wants to obtain safety certification, say in Germany, the OEM can provide a set of data of scenarios on how the vehicle will navigate,” Fritz said. “An OEM can provide a set of data to the German authority, with a set of scenarios to prove the vehicle will navigate in a safe manner under various conditions. By comparing that with the data in the accident database, the German government can say that as long as you avoid 95% of the accidents in that database, you’re certified. That’s actionable from the perspectives of human drivers, insurance, engineering, and visual simulation. The data prove the vehicle is going to behave as expected. The alternative is to drive around, as in the case of autonomous vehicles, and try to justify the accident was not caused by the vehicle, while facing the lawsuit. It does not seem to make sense, but that’s what’s happening today.”

Related Reading
Curbing Automotive Cybersecurity Attacks
A growing number of standards and regulations within the automotive ecosystem promises to save developments costs by fending off cyberattacks.
Software-Defined Vehicles Ready To Roll
New approach could have big effects on cost, safety, security, and time to market.

The post Increased Automotive Data Use Raises Privacy, Security Concerns appeared first on Semiconductor Engineering.

By Adam Kovac, Karen Heyman, and Liz Allan.

India approved the construction of two fabs and a packaging house, for a total investment of about $15.2 billion, according to multiple sources. One fab will be jointly owned by Tata and Taiwan’s Powerchip. The second fab will be a joint investment between CG Power, Japan’s Renesas Electronics, and Thailand’s Stars Microelectronics. Tata will run the packaging facility, as well. India expects these efforts will add 20,000 advanced technology jobs and 60,000 indirect jobs, according to the Times of India. The country has been talking about building a fab for at least the past couple of decades, but funding never materialized.

The U.S. Department of Commerce (DoC) issued a CHIPS Act-based Notice of Funding Opportunity for R&D to establish and accelerate domestic capacity for advanced packaging substrates and substrate materials. The U.S. Secretary of Commerce said the government is prioritizing CHIPS Act funding for projects that will be operational by 2030 and anticipates America will produce 20% of the world’s leading-edge logic chips by the end of the decade.

The top three foundries plan to implement backside power delivery as soon as the 2nm node, setting the stage for faster and more efficient switching in chips, reduced routing congestion, and lower noise across multiple metal layers. But this novel approach to optimizing logic performance depends on advances in lithography, etching, polishing, and bonding processes.

Intel spun out Altera as a standalone FPGA company, the culmination of a rebranding and reorganization of its former Programmable Solutions Group. The move follows Intel’s decision to keep Intel Foundry at arm’s length, with a clean line between the foundry and the company’s processor business.

Multiple new hardware micro-architecture vulnerabilities were published in the latest Common Weakness Enumeration release this week, all related to transient execution (CWE 1420-1423).

The U.S. Office of the National Cyber Director (ONCD) published a technical report calling for the adoption of memory safe programming languages, aiming to reduce the attack surface in cyberspace and anticipate systemic security risk with better diagnostics. The DoC also is seeking information ahead of an inquiry into Chinese-made connected vehicles “to understand the extent of the technology in these cars that can capture wide swaths of data or remotely disable or manipulate connected vehicles.”

Quick links to more news:

Design and Power
Manufacturing and Test
Automotive
Security
Pervasive Computing and AI
Events

Design and Power

Micron began mass production of a new high-bandwidth chip for AI. The company said the HBM3E will be a key component in NVIDIA’s H2000 Tensor Core GPUs, set to begin shipping in the second quarter of 2024. HBM is a key component of 2.5D advanced packages.

Samsung developed a 36GB HBM3E 12H DRAM, saying it sets new records for bandwidth. The company achieved this by using advanced thermal compression non-conductive film, which allowed it to cram 12 layers into the area normally taken up by 8. This is a novel way of increasing DRAM density.

Keysight introduced QuantumPro, a design and simulation tool, plus workflow, for quantum computers. It combines five functionalities into the Advanced Design System (ADS) 2024 platform. Keysight also introduced its AI Data Center Test Platform, which includes pre-packaged benchmarking apps and dataset analysis tools.

Synopsys announced a 1.6T Ethernet IP solution, including 1.6T MAC and PCS Ethernet controllers, 224G Ethernet PHY IP, and verification IP.

Tenstorrent, Japan’s Leading-Edge Semiconductor Technology Center (LSTC) , and Rapidus are co-designing AI chips. LSTC will use Tenstorrent’s RISC-V and Chiplet IP for its forthcoming edge 2nm AI accelerator.

This week’s Systems and Design newsletter features these top stories:

• 2.5D Integration: Big Chip Or Small PCB: Defining whether a 5D device is a PCB shrunk to fit into a package or a chip that extends beyond the limits of a single die can have significant design consequences.
• Commercial Chiplets: Challenges of establishing a commercial chiplet.
• Accellera Preps New Standard For Clock-Domain Crossing: New standard aims to streamline the clock-domain crossing flow.
• Thinking Big: From Chips To Systems: Aart de Geus discusses the shift from chips to systems, next-generation transistors, and what’s required to build multi-die devices.
• Integration challenges for RISC-V: Modifying the source code allows for democratization of design, but it adds some hurdles for design teams (video).

Demand for high-end AI servers is driven by four American companies, which will account for 60% of global demand in 2024, according to Trendforce. NVIDIA is projected to continue leading the market, with AMD closing the gap due its lower cost model.

The EU consortium PREVAIL is accepting design proposals as it seeks to develop next-gen edge-AI technologies. Anchors include CEA-Leti, Fraunhofer-Gesellschaft, imec, and VTT, which will use their 300mm fabrication, design, and test facilities to validate prototypes.

Siemens joined an initiative to expand educational opportunities in the semiconductor space around the world. The Semiconductor Education Alliance was launched by Arm in 2023 and focuses on helping teach skills in IC design and EDA.

Q-CTRL announced partnerships with six firms that it says will expand access to its performance-management software and quantum technologies. Wolfram, Aqarios, and qBraid will integrate Q-CTRL’s Fire Opal technology into their products, while Qblox, Keysight, and Quantware will utilize Q-CTRL’s Boulder Opal hardware system.

NTT, Red Hat, NVIDIA, and Fujitsu teamed up to provide data pipeline acceleration and contain orchestration technologies targeted at real-time AI analysis of massive data sets at the edge.

Manufacturing and Test

The U.S. Department of Energy (DOE)’s Office of Electricity launched the American-Made Silicon Carbide (SiC)  Packaging Prize. This $2.25 million contest invites competitors to propose, design, build, and test state-of-the-art SiC semiconductor packaging prototypes.

Applied Materials introduced products and solutions for patterning issues in the “angstrom era,” including line edge roughness, tip-to-tip spacing limitations, bridge defects, and edge placement errors.

imec reported progress made in EUV processes, masks and metrology in preparation for high-NA EUV. It also identified advanced node lithography and etch related processes that contribute the most to direct emissions of CO2, along with proposed solutions.

proteanTecs will participate in the Arm Total Design ecosystem, which now includes more than 20 companies united around a charter to accelerate and simplify the development of custom SoCs based on Arm Neoverse compute subsystems.

NikkeiAsia took an in-depth look at Japan’s semiconductor ecosystem and concluded it is ripe for revival with investments from TSMC, Samsung, and Micron, among others. TrendForce came to a similar conclusion, pointing to the fast pace of Japan’s resurgence, including the opening of TSMC’s fab.

‍FormFactor closed its sale of its Suzhou and Shanghai companies to Grand Junction Semiconductor for $25M in cash.

The eBeam Initiative celebrated its 15th anniversary and welcomed a new member, FUJIFILM. The group also uncorked its fourth survey of its members technology using deep learning in the photomask-to-wafer manufacturing flow.

Automotive

Apple shuttered its electric car project after 10 years of development. The chaotic effort cost the company billions of dollars, according to The New York Times.

Infineon released new automotive programmable SoCs with fifth-gen human machine interface (HMI) technology, offering improved sensitivity in three packages. The MCU offers up to 84 GPIOs and 384 KB of flash memory. The company also released automotive and industrial-grade 750V G1 discrete SiC MOSFETs aimed at applications such as EV charging, onboard chargers, DC-DC converters, energy, solid state circuit breakers, and data centers.

Cadence expanded its Tensilica IP portfolio to boost computation for automotive sensor fusion applications. Vision, radar, lidar, and AI processing are combined in a single DSP for multi-modal, sensor-based system designs.

Ansys will continue translating fast computing into fast cars, as the company’s partnership with Oracle Red Bull Racing was renewed. The Formula 1 team uses Ansys technology to improve car aerodynamics and ensure the safety of its vehicles.

Lazer Sport adopted Siemens’ Xcelerator portfolio to connect 3D design with 3D printing for prototyping and digital simulation of its sustainable KinetiCore cycling helmet.

The chair of the U.S. Federal Communications Commission (FCC) suggested automakers that sell internet-connected cars should be subject to a telecommunications law aiming to protect domestic violence survivors, reports CNBC. This is due to emerging cases of stalking through vehicle location tracking technology and remote control of functions like locking doors or honking the horn.

BYD‘s CEO said the company does not plan to enter the U.S. market because it is complicated and electrification has slowed down, reports Yahoo Finance. Meanwhile, the first shipment of BYD vehicles arrived in Europe, according to DW News.

Ascent Solar Technologies’ solar module products will fly on NASA’s upcoming Lightweight Integrated Solar Array and AnTenna (LISA-T) mission.

Security

Researchers at Texas A&M University and the University of Delaware proposed the first red-team attack on graph neural network (GNN)-based techniques in hardware security.

A panel of four experts discuss mounting concerns over quantum security, auto architectures, and supply chain resiliency.

Synopsys released its ninth annual Open Source Security and Risk Analysis report, finding that 74% of code bases contained high-risk open-source vulnerabilities, up 54% since last year.

President Biden issued an executive order to prevent the large-scale transfer of Americans’ personal data to countries of concern. Types of data include genomic, biometric, personal health, geolocation, financial, and other personally identifiable information, which bad actors can use to track and scam Americans.

The National Institute of Standards and Technology (NIST) released Cybersecurity Framework (CSF) 2.0 to provide a comprehensive view for managing cybersecurity risk.

The EU Agency for Cybersecurity (ENISA) published a study on best practices for cyber crisis management, saying the geopolitical situation continues to impact the cyber threat landscape and planning for threats and incidents is vital for crisis management.

The U.S. Department of Energy (DOE) announced $45 million to protect the energy sector from cyberattacks.

The National Security Agency (NSA), the Federal Bureau of Investigation (FBI), and others published an advisory on Russian cyber actors using compromised routers.  Also the Cybersecurity and Infrastructure Security Agency (CISA), the UK National Cyber Security Centre (NCSC), and partners advised of tactics used by Russian Foreign Intelligence Service cyber actors to gain initial access into a cloud environment.

CISA, the FBI, and the Department of Health and Human Services (HHS) updated an advisory concerning the ALPHV Blackcat ransomware as a service (RaaS), which primarily targets the healthcare sector.

CISA also published a guide to support university cybersecurity clinics and issued other alerts.

Pervasive Computing and AI

Renesas expanded its RZ family of MPUs with a single-chip AI accelerator that offers 10 TOPS per watt power efficiency and delivers AI inference performance of up to 80 TOPS without a cooling fan. The chip is aimed at next-gen robotics with vision AI and real-time control.

Infineon launched dual-phase power modules to help data centers meet the power demands of AI GPU platforms. The company also released a family of solid-state isolators to deliver faster switching with up to 70% lower power dissipation.

Fig. 1: Infineon’s dual phase power modules: Source: Infineon

Amber Semiconductor announced a reference design for brushless motor applications using its AC to DC conversion semiconductor system to power ST‘s STM32 MCUs.

Micron released its universal flash storage (UFS) 4.0 package at just 9×13 mm, built on 232-layer 3D NAND and offering up to 1 terabyte capacity to enable next-gen phone designs and larger batteries.

LG and Meta teamed up to develop extended reality (XR) products, content, services, and platforms within the virtual space.

Microsoft and Mistral AI partnered to accelerate AI innovation and to develop and deploy Mistral’s next-gen large language models (LLMs).

Microsoft’s vice chair and president announced the company’s AI access principles, governing how it will operate AI datacenter infrastructure and other AI assets around the world.

Singtel and VMware partnered to enable enterprises to manage their connectivity and cloud infrastructure through the Singtel Paragon platform for 5G and edge cloud.

Keysight was selected as the Test Partner for the Deutsche Telekom Satellite NB-IoT Early Adopter Program, providing an end-to-end NB-IoT NTN testbed that allows designers and developers to validate reference designs for solutions using 3GPP Release 17 (Rel-17) NTN standards.

Global server shipments are predicted to increase by 2.05% in 2024, with AI servers accounting for about 12%, reports TrendForce. Also, the smartphone camera lens market is expected to rebound in 2024 with 3.8% growth driven by AI-smartphones, to reach about 4.22 billion units, reports TrendForce.

Yole released a smartphone camera comparison report with a focus on iPhone evolution and analysis of the structure, design, and teardown of each camera module, along with the CIS dimensions, technology node, and manufacturing processes.

Counterpoint released a number of 2023 reports on smartphone shipments by country and operator migrations to 5G.

Events

Find upcoming chip industry events here, including:

Upcoming webinars are here, including topics such as digital twins, power challenges in data centers, and designing for 112G interface compliance.

Further Reading and Newsletters

Read the latest special reports and top stories, or check out the latest newsletters:

Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials
Automotive, Security and Pervasive Computing

The post Chip Industry Week In Review appeared first on Semiconductor Engineering.

Experts at the Table: Semiconductor Engineering sat down to talk about the challenges of establishing a commercial chiplet ecosystem with Frank Schirrmeister, vice president solutions and business development at Arteris; Mayank Bhatnagar, product marketing director in the Silicon Solutions Group at Cadence; Paul Karazuba, vice president of marketing at Expedera; Stephen Slater, EDA product management/integrating manager at Keysight; Kevin Rinebold, account technology manager for advanced packaging solutions at Siemens EDA; and Mick Posner, vice president of product management for high-performance computing IP solutions at Synopsys. What follows are excerpts of that discussion.

L-R: Arteris’ Schirrmeister, Cadence’s Bhatnagar, Expedera’s Karazuba, Keysight’s Slater, Siemens EDA’s Rinebold, and Synopsys’ Posner.

SE: There’s a lot of buzz and activity around every aspect of chiplets today. What is your impression of where the commercial chiplet ecosystem stands today?

Schirrmeister: There’s a lot of interest today in an open chiplet ecosystem, but we are probably still quite a bit away from true openness. The proprietary versions of chiplets are alive and kicking out there. We see them in designs. We vendors are all supporting those to make it reality, like the UCIe proponents, but it will take some time to get to a fully open ecosystem. It’s probably at least three to five years before we get to a PCI Express type exchange environment.

Bhatnagar: The commercial chiplet ecosystem is at a very early stage. Many companies are providing chiplets, are designing them, and they’re shipping products — but they’re still single-vendor products, where the same company is designing all the pieces. I hope that with the advancements the UCIe standard is making, and with more standardization, we eventually can get to a marketplace-like environment for chiplets. We are not there.

Karazuba: The commercialization of homogeneous chiplets is pretty well understood by groups like AMD. But for the commercialization of heterogeneous chiplets, which is chiplets from multiple suppliers, there are still a lot of questions out there about that.

Slater: We participate in a lot of the board discussions, and attend industry events like TSMC’s OIP, and there’s a lot of excitement out there at the moment. I see a lot of even midsize and small customers starting to think about their development plans for what chiplet should be. I do think those that are going to be successful first will be those that are within a singular foundry ecosystem like TSMC’s. Today if you’re selecting your IP, you’ve got a variety of ways to be able to pick and choose which IP, see what’s been taped out before, how successful it’s been so you have a way to manage your risk and your costs as you’re putting things together. What we’ll see in the future will be that now you have a choice. Are you purchasing IP, or are you purchasing chiplets? Crucially, it’s all coming from the same foundry and put together in the same manner. The technical considerations of things like UCIe standard packaging versus advanced packaging, and the analysis tool sets for high-speed simulation, as well as for things like thermal, are going to just become that much more important.

Rinebold: I’ve been doing this about 30 years, so I can date back to some of the very earliest days of multi-chip modules and such. When we talk about the ecosystem, there are plenty of examples out there today where we see HBM and logic getting combined at the interposer level. This works if you believe HBM is a chiplet, and that’s a whole other argument. Some would argue that HBM falls into that category. The idea of a true LEGO, snap-together mix and match of chiplets continues to be aspirational for the mainstream market, but there are some business impediments that need to get addressed. Again, there are exceptions in some of the single-vendor solutions, where it’s more or less homogeneous integration, or an entirely vertically integrated type of environment where single vendors are integrating their own chiplets into some pretty impressive packages.

Posner: Aspirational is the word we use for an open ecosystem. I’m going to be a little bit more of a downer by saying I believe it’s 5 to 10 years out. Is it possible? Absolutely. But the biggest issue we see at the moment is a huge knowledge gap in what that really means. And as technology companies become more educated on really what that means, we’ll find that there will be some acceleration in adoption. But within what we call ‘captive’ — within a single company or a micro-ecosystem — we’re seeing multi-die systems pick up.

SE: Is it possible to define the pieces we have today from a technology point of view, to make a commercial chiplet ecosystem a reality?

Rinebold: What’s encouraging is the development of standards. There’s some adoption. We’ve already mentioned UCIe for some of the die-to-die protocols. Organizations like JEDEC announced the extension of their JEP30 PartModel format into the chiplet ecosystem to incorporate chiplet-style data. Think about this as an electronic data sheet. A lot of this work has been incorporated into the CDX working group under Open Compute. That’s encouraging. There were some comments a little bit earlier about having an open marketplace. I would agree we’re probably 3 to 10 years away from that coming to fruition. The underlying framework and infrastructure is there, but a lot of the licensing and distribution issues have to get resolved before you see any type of broad adoption.

Posner: The infrastructure is available. The EDA tools to create, to package, to analyze, to simulate, to manufacture — those tools are all there. The intellectual property that sits around it, either UCIe or some of the more traditional die-to-die interfaces, all of that’s there. What’s not established are full methodology and flows that lead to interoperability. Everything within captive is possible, but a broader ecosystem, a marketplace, is going to require silicon interoperability, simulation, packaging, all of that. That’s the area that we believe is missing — and still building.

Schirrmeister: Do we know what’s required? We probably can define that reasonably well. If the vision is an open ecosystem with IP on chiplets that you can just plug together like LEGO blocks, then the IP industry informs us of what’s required, and then there are some gaps on top of them. I hear people from the hard-coded IP world talking about the equivalent of PDKs for chiplets, but today’s IP ecosystem and the IP deliverables are informing us it doesn’t work like LEGO blocks yet. We are improving every year. But this whole, ‘I take my whiteboard and then everything just magically functions together’ is not what we have today. We need to think really hard about what the additional challenges are when you disaggregate that into chiplets and protocols. Then you get big systemic issues to deal with, like how do you deal with coherency across chiplets? It was challenging enough to get it done on a chip. Now you potentially have to deal with other partnerships you don’t even own. This is not a captive environment in an open ecosystem. That makes it very challenging, and it creates job security for at least 5 to 10 years.

Bhatnagar: On the technical side, what’s going well is adoption. We can see big companies like Intel, and then of course, IP providers like us and Synopsys. Everybody’s working toward standardizing chiplet integration, and that is working very well. EDA tools are also coming up to support that. But we are still very far from a marketplace because there are many issues that are not sorted out, like licensing and a few other things that need a bit more time.

Slater: The standards bodies and networking groups have excited a lot of people, and we’re getting a broad set of customers that are coming along. And one point I was thinking, is this only for very high-end compute? From the companies that I see presenting in those types of forums, it’s even companies working in automotive or aerospace/defense, planning out their future for the next 10 years or more. In the automotive case, it was a company that was thinking about creating chiplets for internal consumption — so maybe reorganizing how they look at creating many different variations or evolutions of their products, trying to do it as more modular chiplet types of blocks. ‘If we take the microprocessor part of it, would we sell that as a chiplet externally for other customers to integrate together into a bigger design?’ For me, the aha moment was seeing how broad the application would be. I do think that the standards work has been moving very fast, and that’s worked really well. For instance, at Keysight EDA, we just released a chiplet PHY designer. It’s a simulation for the high-speed digital link for UCIe, and that only comes about by having a standard that’s published, so an EDA company can take a look at it and realize what they need to do with it. The EDA tools are ready to handle these kinds of things. And maybe then, on to the last point is, in order to share the IP, in order to ensure that it’s available, database and process management is going to become all the more important. You need to keep track of which chip is made on which process, and be able to make it available inside the company to other potential users of that.

SE: What’s in place today from a business perspective, and what still needs to be worked out?

Karazuba: From a business perspective, speaking strictly of heterogeneous chiplets, I don’t think there’s anything really in place. Let me qualify that by asking, ‘Who is responsible for warranty? Who is responsible for testing? Who is responsible for faults? Who is responsible for supply chain?’ With homogeneous chiplets or monolithic silicon, that’s understood because that’s the way that this industry has been doing business since its inception. But when you talk about chiplets that are coming from multiple suppliers, with multiple IPs — and perhaps different interfaces, made in multiple fabs, then constructed by a third party, put together by a third party, tested by a fourth party, and then shipped — what happens when something goes wrong? Who do you point the finger at? Who do you go to and talk to? If a particular chiplet isn’t functioning as intended, it’s not necessarily that chiplet that’s bad. It may be the interface on another chiplet, or on a hub, whatever it might be. We’re going to get there, but right now that’s not understood. It’s not understood who is going to be responsible for things such as that. Is it the multi-chip module manufacturer, or is it the person buying it? I fear a return to the Wintel issue, where the chipmaker points to the OS maker, which points at the hardware maker, which points at the chipmaker. Understanding of the commercial side is is a real barrier to chiplets being adopted. Granted, the technical is much more difficult than the commercial, but I have no doubt the engineers will get there quicker than the business people.

Rinebold: I completely agree. What are the repercussions, warranty-related issues, things like that? I’d also go one step further. If you look at some of the larger silicon foundries right now, there is some concern about taking third-party wafers into their facilities to integrate in some type of heterogeneous, chiplet-type package. There are a lot of business and logistical issues that have to get addressed first. The technical stuff will happen quickly. It’s just a lot of these licensing- and distribution-type issues that need to get resolved. The other thing I want to back up to involves customers in the defense/industrial space. The trust and traceability and the province tracking of IP is going to be key for them, because they have so much expectation of multi-die or chiplet-type packaging as an alternative to monolithic scaling. Just look at all the government programs out there right now, with RESHAPE [Reshore Ecosystem for Secure Heterogeneous Advanced Packaging Electronics] and NGMM [Next-Generation Microelectronics Manufacturing] and such. They’re all in on this chiplet perspective, but they’re going to require a lot of security measures to understand who has touched the IP, where it comes from, how to you verify that.

Posner: Micro-ecosystems are forming because of all these challenges. If you naively think you can just go pick a die off the shelf and put it into your device, how do you warranty that? Who owns it? These micro-ecosystems are building up to fundamentally sort that out. So within a couple of different companies, be it automotive or high-performance compute, they’ll come to terms that are acceptable across all of them. And it’s these micro-ecosystems that are really going to end up driving open chiplets, and I think it’s going to be an organic type of growth. Chiplets are available for a specific application today, but we have this vision that someone else could use it, and we see that with the multiple modes being built into the dies. One mode is, ‘I’m connecting to myself. It’s a very tight, low-latency link.’ But I have this vision in the future that I’m going to need to have an interface or protocol that is more open and uses standard available stacks, and which can be bought off the shelf and integrated. That’s one side of the logistics. I want to mention two more things. It is possible to do interoperability across nodes. We demonstrated our TSMC N3 UCIe with Intel’s in-house UCIe, all put together on an Intel process. This was two separate companies working together, showing the first physical interoperability, so it’s possible. But going forward that’s still just a small part of the overall effort. In the IP space we’ve lived with an IP model of, ‘Build once, sell many.’ With the chiplet marketplace, unless there is a revenue stream from that chiplet, it will break that model. Companies think, ‘I only have to buy the IP once, and then I’m selling my silicon.’ But the infrastructure, the resources that are required to build all of this does not go away. There has to be money at the end of that tunnel for all of these different companies to be investing.

Schirrmeister: Mick is 100% right, but we may have a definition issue here with what we really mean by an ‘open’ chiplet ecosystem. I have two distinct conversations when I talk to partners and customers. On the one hand, you have board designers who are doing more and more integration, and they look at you with a wrinkled forehead and say, ‘We’ve been doing this for years. What are you talking about?’ It may not have been 3D-IC in the classic sense of all items, but they say, ‘Yeah, there are issues with warranties, and the user figures it out.’ The board people arrive from one side of the equation at chiplets because that’s the next evolution of integration. You need to be very efficient. That’s not what we call an open ecosystem of chiplets here. The idea is that you have this marketplace to mix things up, and you have the economies of scale by selling the same chiplet to multiple people. That’s really what the chip designers are thinking about, and some of them think even further because if you do it all in true 3D-IC fashion, then you actually have to co-design those chiplets in a way, and that’s a whole other dimension that needs to be sorted out. To pick a little bit on the big companies that have board and chip design groups in house, you see this even within the messaging of these companies. You have people who come from the board side, and for them it’s not a solved problem. It always has been challenging, but they’re going to take it to the next level. The chip guys are looking at this from a perspective of one interface, like PCI Express, now being UCIe. And then I think about this because the networks on chip need to become super NoCs across chiplets, which poses its own challenges. And that all needs to work together. But those are really chiplets designed for the purpose of being in a chiplet ecosystem. And to that end, Mick’s estimation of longer than five years is probably correct because those purpose-built chiplets, for the purpose of being in an open ecosystem, have all these challenges the board guys have already been dealing with for quite some time. They’re now ‘just getting smaller’ in the amount of integration they do.

Slater: When you put all these chiplets together and start to do that integration, in what order do you start placing the components down? You don’t want to throw away one very expensive chiplet because there was an issue with one of the smaller cheaper ones. So, there are now a lot of thoughts about how to go about doing almost like unit tests on individual chiplets first, but then you want to do some form of system test as you go along. That’s definitely something we need to think about. On the business front,  who is going to be most interested in purchasing a chiplet-style solution. It comes down to whether you have a yield problem. If your chips are getting to the size where you have yield concerns, then definitely it makes sense to think about using chiplets and breaking it up into smaller pieces. Not everything scales, so why move to the lowest process node when you could purchase something at a different process node that has less risk and costs less to manufacture, and then put it all together. The ones that have been successful so far — the big companies like Intel, AMD — were already driven to that edge. The chips got to a size that couldn’t fit on the reticle. We think about how many companies fit into that category, and that will factor into whether or not the cost and risk is worth it for them.

Bhatnagar: From a business perspective, what is really important is the standardization. Inside of the chiplets is fine, but how it impacts other chiplets around it is important. We would like to be able to make something and sell many copies of it. But if there is no standardization, then either we are taking a gamble by going for one thing and assuming everybody moves to it, or we make multiple versions of the same thing and that adds extra costs. To really justify a business case for any chiplet or, or any sort of IP with the chiplet, the standardization is key for the electrical interconnect, packaging, and all other aspects of a system.

Fig. 1:  A chiplet design. Source: Cadence. 

Related Reading
Chiplets: 2023 (EBook)
What chiplets are, what they are being used for today, and what they will be used for in the future.
Proprietary Vs. Commercial Chiplets
Who wins, who loses, and where are the big challenges for multi-vendor heterogeneous integration.

The post Commercial Chiplet Ecosystem May Be A Decade Away appeared first on Semiconductor Engineering.

For more than half a century, silicon has been the bedrock of power electronics. Yet as silicon meets its physical limitations in higher-power, higher-temperature applications, the industry’s relentless pursuit of more efficient power systems has ushered in the wide bandgap (WBG) semiconductors era. The global WBG semiconductors market reached $1.6 billion in 2022, with an estimated CAGR of $13% for the next 8-year period. The adoption of WBG semiconductors, notably silicon carbide (SiC) and gallium nitride (GaN), is now setting new benchmarks for performance in power systems across automotive, industrial, and energy sectors. What impact will WBG semiconductors have on power electronics (PE) trends in 2024, and how are they redefining the design and simulation workflows for the next decade?

The catalyst for change: Wide bandgap

The term ‘bandgap’ refers to the energy difference between a material’s insulating and conducting states, a critical factor determining its electrical conductivity.

As shown in figure 1, with its wide bandgap, Gallium Nitride (GaN) exemplifies the three key advantages this property can offer.

Fig. 1: Wide bandgap semiconductor properties.

• Faster switching speeds: One of the most significant benefits of GaN’s wide bandgap is its contribution to faster switching speeds. The electron mobility in GaN is around 2,000 cm²/Vs, enabling switching frequencies up to 10 times higher than silicon. A higher switching speed translates into reduced switching losses, making the overall designs more compact and efficient.

Fig. 2: Switching speeds of SiC and GaN.

• Higher thermal resistance: With a thermal conductivity of 2 W/cmK, GaN can dissipate heat and operate at temperatures up to 200°C efficiently. This resilience enables more effective thermal management at high temperatures and extreme conditions.
• Higher voltages: With an electric breakdown field of 3.3 MV/cm, GaN can withstand almost 10 times silicon’s voltage.

GaN and other wide-bandgap semiconductors offer solutions for high-power, high-frequency, and high-temperature applications with improved energy efficiency and design flexibility.

Emerging challenges in power electronics simulation

The wider adoption of wide bandgap (WBG) semiconductors, including silicon carbide (SiC) and gallium nitride (GaN), sets new standards in the design of Switched Mode Power Supplies (SMPS) – power efficiency, compactness, and lighter weight.

However, the higher switching speeds of GaN and SiC demand more sophisticated design considerations. Power electronics engineers must manage electromagnetic interference (EMI) and optimize thermal performance to ensure reliability and functionality. Layout parasitics, for instance, can lead to voltage spikes in the presence of high di/dt values. Power electronics engineers face the following pressing questions:

• How can we guarantee reliability for mission-critical applications across a wider range of operating temperatures?
• What are the essential practices for understanding and predicting EMI and noise?
• What tools can we employ to create robust thermal models for comprehensive system-level analysis?

To navigate these complexities, engineers need advanced simulation solutions to address layout parasitic effects effectively and come with robust thermal analysis.

Fig. 3: Thermal analysis at board and schematic levels using Keysight’s PEPro.

Key impacts of WBG semiconductors: From EVs to renewable energy

Electric vehicles (EVs): As global EV sales are projected to increase by 21% in 2024, the power efficiency of automotive power electronics is paramount – every additional percentage is a big win. GaN enables more compact and efficient designs of onboard chargers and traction inverters, extending driving ranges by up to 6%.

Data centers: The digital economy’s expansion brings a surge in data center energy consumption, with the U.S. expected to require an additional 39 gigawatts over the next five years—equivalent to powering around 32 million homes. Wide bandgap semiconductors may be key to addressing this challenge by enabling higher server densities and reducing energy consumption and carbon emissions. Specifically, the implementation of GaN transistors in data center infrastructure can lead to a reduction of 100 metric tons of CO2 emissions for every 10 racks annually. This efficiency gain is particularly relevant as the computational and power demands of artificial intelligence (AI) applications soar, potentially tripling the racks’ power density.

Renewable energy: Wide bandgap semiconductors allow for more reliable power output and cost-effective solutions in both residential and commercial renewable energy storage systems. For instance, GaN transistors could achieve four times less power loss than traditional silicon-based power solutions.

The road ahead in the era of WBG semiconductors

GaN and SiC represent a new wave of material innovation to elevate the efficiencies of power electronics and redefine how we power our world. As the applications for WBG semiconductors expand, Keysight empowers our customers with a unified simulation environment to design reliable and long-lasting electronic systems under various operating conditions.

The post What’s Next For Power Electronics? Beyond Silicon appeared first on Semiconductor Engineering.

Siemens’ John McMillan digs into physical verification maturity for high-density advanced packaging (HDAP) designs and major differences in the LVS verification flow compared to the well-established process for SoCs.

Synopsys’ Varun Shah identifies why a cloud adoption framework is key to getting the most out of deploying EDA tools in the cloud, including by ensuring that different types of necessary compute are accessible for all stages of the design cycle.

Cadence’s Reela Samuel suggests that a chiplet-based approach will provide improved performance and reduced complexity for the automotive sector, enabling OEMs to construct a robust yet flexible electronic architecture.

Keysight’s Emily Yan finds that today’s chip design landscape is facing challenges reminiscent of those encountered by the Large Hadron Collider in managing data volume, version control, and global collaboration.

Ansys’ Raha Vafaei explains why the finite-difference time-domain (FDTD) method, an algorithmic approach to solving Maxwell’s equations, is key for modeling nanophotonic devices, processes, and materials.

Arm’s Ed Player explains the different components of the Common Microcontroller Software Interface Standard (CMSIS) to help identify which are useful for particular Arm-based microcontroller projects.

SEMI’s Mark da Silva, Nishita Rao and Karim Somani check out the state of digital twins in semiconductor manufacturing and challenges such as the need for standardization and communication between different digital twins.

Plus, check out the blogs featured in the latest Low Power-High Performance newsletter:

Rambus’ Lou Ternullo looks at why performance demands of generative AI and other advanced workloads will require new architectural solutions enabled by CXL.

Ansys’ Raha Vafaei shines a light on how the evolution of photonics engineering will encompass novel materials and cutting-edge techniques.

Siemens’ Keith Felton explains why embracing emerging approaches is essential for crafting IC packages that address the evolving demands of sustainability, technology, and consumer preferences.

Cadence’s Mark Seymour lays out how CFD simulation software can predict time-dependent aspects and various failure scenarios for data center managers.

Arm’s Adnan Al-Sinan and Gian Marco Iodice point out that LLMs already run well on small devices, and that will only improve as models become smaller and more sophisticated.

Keysight’s Roberto Piacentini Filho shows how a modular approach can improve yield, reduce cost, and improve PPA/C.

Quadric’s Steve Roddy finds that smart local memory in an AI/ML subsystem solves SoC bottlenecks.

Synopsys’ Ian Land, Kenneth Larsen, and Rob Aitken detail why the traditional approach using monolithic system-on-chips (SoCs) falls short when addressing the complex needs of modern systems.

The post Blog Review: Feb. 21 appeared first on Semiconductor Engineering.