Cadence’s Reela Samuel explores the critical role of PCIe 6.0 equalization in maintaining signal integrity and solutions to mitigate verification challenges, such as creating checkers to verify all symbols of TS0, ensuring the correct functioning of scrambling, and monitoring phase and LTSSM state transitions.

Siemens’ John McMillan introduces an advanced packaging flow for Intel’s Embedded Multi-die Interconnect Bridge (EMIB) technology, including technical challenges, design methodologies, and the integration of EMIBs in system-level package designs.

Synopsys’ Dustin Todd checks out what’s next for the U.S. CHIPS and Science Act, including the establishment of the National Semiconductor Technology Center and the allocation of $13 billion for research and development efforts.

Keysight’s Roberto Piacentini Filho explores the challenges of managing the large design files and massive volumes of data involved in a modern chip design project, which can take up as much as a terabyte of disk space and involve hundreds of thousands of files.

Arm’s Sandeep Mistry shows how ML models developed for mobile computer vision applications and requiring tens to hundreds of millions of multiply-accumulate (MACs) operations per inference can be deployed to a modern microcontroller.

Ansys’ Aliyah Mallak explores an effort to manufacture biotech products in microgravity and how simulation helps ensure payloads containing delicate, temperature-sensitive spore samples and bioreactors make it safely to the International Space Station or low Earth orbit safely.

Micron Technology’s Amit Srivastava, ULVAC’s Brian Coppa, and SEMI’s Mark da Silva suggest tackling corporate sustainability goals with a bottom-up approach that leverages various sensing technologies, at the cleanroom, sub-fab, and facilities levels for both greenfield and brownfield device-making facilities, to enable predictive analytics.

And don’t miss the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

Amkor’s JeongMin Ju shows how to prevent critical failures in copper RDLs caused by overcurrent-induced fusing.

Synopsys’ Al Blais discusses curvilinear checking and fracture requirements for the MULTIGON era.

Lam Research’s Dempsey Deng compares the parasitic capacitance of a 6F² honeycomb DRAM device to a 4F² VCAT DRAM structure.

Brewer Science’s Jessica Albright covers debonding methods, thermal, topography, adhesion, and thickness variation.

SEMI’s John Cooney reviews a fireside chat between the President of SEMI Americas and the U.S. Under Secretary of State for Economic Growth, Energy, and the Environment on securing supply chains.

The post Blog Review: Aug. 21 appeared first on Semiconductor Engineering.

SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how competitive, and potentially lucrative, the HBM market is becoming. SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at the base of the HBM stack.

Intel assembled the industry’s first high-NA EUV lithography system. “Compared to 0.33NA EUV, high-NA EUV (or 0.55NA EUV) can deliver higher imaging contrast for similar features, which enables less light per exposure, thereby reducing the time required to print each layer and increasing wafer output,” Intel said.

Fig. 1: Bigger iron — Intel’s brand new high-NA EUV machinery. Source: Intel

Samsung is slated to receive $6.4 billion in CHIPS ACT funding from the U.S. Department of Commerce (DoC) as part of a $40 billion expansion of its Austin, Texas, manufacturing facility, along with an R&D fab, a pair of leading-edge logic fabs, and an advanced packaging plant in nearby Taylor, Texas.

Micron and the U.S. government next week will announce $6.1 billion in CHIPS Act funding for the development of advanced memory chips in New York and Idaho, according to AP News.

Cadence unveiled its Palladium Z3 Emulation and Protium X3 FPGA Prototyping systems, targeted at multi-billion-gate designs with 2X increase in capacity and a 1.5X performance increase compared to previous-generation systems. Cadence also teamed up with MemVerge to enable seamless support for AWS Spot instances for long-running high-memory EDA jobs, and extended its hybrid cloud environment solutions through a collaboration with NetApp.

Fig. 2: At CadenceLive Silicon Valley, NVIDIA CEO Jensen Huang (r.) discussed accelerated computing and generative AI with Cadence CEO Anirudh Devgan. Source: Semiconductor Engineering

Quick links to more news:

Global
Markets and Money
In-Depth
Security
Education and Workforce
Product and Standards
Research
Quantum
Events
Further Reading

Global

After Taiwan’s recent 7.2 magnitude earthquake, TSMC reached more the 70% tool recovery in its fabs within the first 10 hours and full recovery by the end of the third day, according to this week’s earnings call. Some wafers in process were scrapped but the company expects the lost production to be recovered in the second quarter.  Also in the call, TSMC said they expect their “customers to share some of the higher cost” of the overseas fabs and higher electricity costs.

Advantest‘s regional headquarters in Taiwan donated $2.2 million New Taiwan dollars ($680,000 US) for aid to victims and reconstruction efforts related to the Taiwan earthquake that struck on April 3.

Japan’s exports grew by more than 7% YoY in March, driven by an 11.3% increase in shipments of electronics and semiconductor manufacturing equipment, much of it to China, according to NikkeiAsia.

China‘s IC output grew 40% in the first quarter, primarily driven by EVs and smartphones, according to the South China Morning Post.

In the U.S., the Biden Administration released a notice of funding opportunity of $50 million targeted at small businesses pursuing advances in metrology research and technology. Also, the U.S. Department of Energy announced a $33 million funding opportunity for smart manufacturing technologies.

Germany‘s Fraunhofer IIS launched its On-Board Processor (FOBP) for the German Space Agency’s Heinrich Hertz communication satellite. FOBP can be controlled and reprogrammed from Earth and will be used to investigate creation of hybrid communication networks.

Markets and Money

RISC-V startup Rivos raised more than $250 million in capital investments to tape out its first power-optimized chips for data analytics and generative AI applications.

Silvaco filed to go public on Nasdaq. The company also received a $5 million convertible note investment from Microchip.

Microchip acquired Neuronix AI Labs to provide AI-enabled FPGA solutions for large-scale, high-performance edge applications.

The advanced packaging market saw a modest 4% increase in revenues in Q4 2023 versus the previous quarter, with a projected decline of 13% QoQ in the first quarter of 2024, reports Yole. Overall, the market is expected to increase from $38 billion in 2023 to $69.5 billion in 2029 with a CAGR of 10.7%.

TSMC’s CoWoS total capacity will increase by 150% in 2024 due to demand for NVIDIA’s Blackwell Platform, reports TrendForce.

ASML saw a nearly 40% drop in new litho equipment sales QoQ in Q1 2024 and a 61% drop in net bookings as manufacturers reduced investments in new capital equipment during the recent semiconductor market slump.

Global PC shipments rose about 3% YoY in Q1 2024, and that same growth is expected for full year 2024, reports Counterpoint. Manufacturers are predicted to promote AI PCs as semiconductor companies prepare to launch SoCs featuring higher TOPS.

The GenAI smartphone market share is predicted to reach 11% by 2024 and 43% by 2027, reports Counterpoint. Samsung likely will lead in 2024, but Apple may overtake it in 2025.

The RF GaN market is expected to exceed $2 billion by 2029, fueled by the defense and telecom infrastructure sectors, reports Yole.

In-Depth

Semiconductor Engineering published its Manufacturing, Packaging & Materials newsletter this week. Top articles include:

• Electromigration Concerns Grow In Advanced Packages
• What Works Best For Chiplets
• Enabling Advanced Devices With Atomic Layer Processes

Plus, check out these new stories and tech talks:

• Architecting Chips For High-Performance Computing
• Future-Proofing Automotive V2X
• Secure Movement Of Data In Test
• Challenges With Chiplets and Power Delivery

Security

In security research:

• Seoul National University, Sandia National Laboratories, Texas A&M University, and Applied Materials demonstrated a memristor crossbar architecture for encryption and decryption.
• Robert Bosch, Forschungszentrum Julich, and Newcastle University investigated techniques for error detection and correction in in-memory computing.
• The University of Florida introduced an automated framework that can help identify security assets for a design at the register-transfer level (RTL).

DARPA conducted successful in-air tests of AI flying an F-16 autonomously versus a human-piloted F-16 in visual-range combat scenarios.

The National Security Agency’s Artificial Intelligence Security Center (NSA AISC) published joint guidance on deploying AI systems securely with the Cybersecurity and Infrastructure Security Agency (CISA), the Federal Bureau of Investigation (FBI), and international partners. CISA also issued other alerts.

Products and Standards

Samsung uncorked LPDDR5X DRAM built on a 12nm process that supports up to 10.7 Gbps and expands the single package capacity of mobile DRAM up to 32 GB.

Keysight revealed its next-generation RF circuit simulation tool that supports multi-physics co-design of circuit, electromagnetic, and electrothermal simulations across Cadence, Synopsys, and Keysight platforms.

Renesas released its FemtoClock family of ultra-low jitter clock generators and jitter attenuators with 8 and 12 outputs, enabling clock tree designs for high-speed interconnect systems in telecom and data center switches, routers, medical imaging, and more.

Movellus expanded its droop response solutions with Aeonic Generate AWM3, which responds to voltage droops within 1 to 2 clock cycles while providing enhanced observability for droop profiling and enabling fine-grained dynamic frequency scaling.

Efabless announced the second version of its Python-based open-source EDA software for construction of customizable flows using proprietary or open-source tools.

Faraday Technology licensed Arm’s Cortex-A720AE IP to use in the development of AI-enabled vehicle ASICs. Also, Untether AI teamed up with Arm to enable its inference acceleration technology to be implemented alongside the latest-generation Automotive Enhanced technology from Arm for ADAS and autonomous vehicle applications.

FOXESS used Infineon’s 1,200V CoolSiC MOSFETs and EiceDRIVER gate drivers for industrial energy storage applications, aiming to promote green energy.

Emotors adopted Siemens’ Simcenter solutions for NVH testing of next-gen automotive e-drives.

SiTime debuted a family of clock generators for AI datacenter applications with clock, oscillator, and resonator in an integrated chip.

JEDEC published the JESD79-5C DDR5 SDRAM standard, which includes a DRAM data integrity improvement called Per-Row Activation Counting (PRAC) that precisely counts DRAM activations on a wordline granularity and alerts the system to pause traffic and designate time for mitigation measures when an excessive number of activations are detected.

The LoRa Alliance launched its roadmap for the development of the LoRaWAN open standard for IoT communications, referring to long-range radio (LoRa) low-power wide-area networks (LPWANs).

Education and Workforce

Texas A&M introduced a new Master of Science program for microelectronics and semiconductors, which will begin in fall 2025.

The Cornell NanoScale Science and Technology Facility (CNF) is partnering with Tompkins Cortland Community College and Penn State to offer a free Microelectronics and Nanomanufacturing Certificate Program to veterans and their dependents.

Eindhoven University of Technology (TU/e) has more than 700 researchers and 25 research group focused on the chip industry, but the number is projected to grow significantly due to the Dutch government’s recent investment.

Research

Intel announced a large-scale neuromorphic system based on its Loihi 2 processor. Initially deployed at Sandia National Laboratories, it aims to support research for future brain-inspired AI. Intel is also collaborating with Seekr on next-gen LLM and foundation models.

Los Alamos National Lab, HPE, and NVIDIA collaborated on the design and installation of Venado, the Lab’s new supercomputer. “Venado adds to our cutting-edge supercomputing that advances national security and basic research, and it will accelerate how we integrate artificial intelligence into meeting those challenges,” said Thom Mason, director of Los Alamos National Laboratory in a release.

Penn State is partnering with Morgan Advanced Materials on a five-year, multi-million-dollar research project to advance silicon carbide (SiC) technology. Morgan will become a founding member of the Penn State Silicon Carbide Innovation Alliance. Also, Coherent secured CHIPS Act funding of $15 million for research into high-voltage, high-power silicon carbide and single-crystal diamond semiconductors.

Oak Ridge National Laboratory (ORNL) researchers found a more efficient way to extract lithium from waste liquids leached from mining sites, oil fields, and used batteries.

Quantum

Quantinuum said it reached an inherent 99.9% 2-qubit gate fidelity in its commercial quantum computer, a point at which quantum error correction protocols can be used to greatly reduce error rates.

D-Wave Quantum uncorked a fast-anneal feature to speed up computations on its quantum processing units, which reduces the impact of external disturbances.

MIT researchers outlined a new conceptual model for a quantum computer that aims to make writing code for them easier.

SLAC National Accelerator Laboratory, Stanford University, Max Planck Institute of Quantum Optics, Ludwig-Maximilians-Universitat Munich, and Instituto de Ciencia de Materiales de Madrid researchers proposed a method that harnesses the structure of light to tweak the properties of quantum materials.

Events

Find upcoming chip industry events here, including:

Upcoming webinars are here.

Further Reading

Read the latest special reports and top stories, or check out the latest newsletters:

Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials
Automotive, Security and Pervasive Computing

The post Chip Industry Week In Review appeared first on Semiconductor Engineering.

SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how competitive, and potentially lucrative, the HBM market is becoming. SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at the base of the HBM stack.

Intel assembled the industry’s first high-NA EUV lithography system. “Compared to 0.33NA EUV, high-NA EUV (or 0.55NA EUV) can deliver higher imaging contrast for similar features, which enables less light per exposure, thereby reducing the time required to print each layer and increasing wafer output,” Intel said.

Fig. 1: Bigger iron — Intel’s brand new high-NA EUV machinery. Source: Intel

Samsung is slated to receive $6.4 billion in CHIPS ACT funding from the U.S. Department of Commerce (DoC) as part of a $40 billion expansion of its Austin, Texas, manufacturing facility, along with an R&D fab, a pair of leading-edge logic fabs, and an advanced packaging plant in nearby Taylor, Texas.

Micron and the U.S. government next week will announce $6.1 billion in CHIPS Act funding for the development of advanced memory chips in New York and Idaho, according to AP News.

Cadence unveiled its Palladium Z3 Emulation and Protium X3 FPGA Prototyping systems, targeted at multi-billion-gate designs with 2X increase in capacity and a 1.5X performance increase compared to previous-generation systems. Cadence also teamed up with MemVerge to enable seamless support for AWS Spot instances for long-running high-memory EDA jobs, and extended its hybrid cloud environment solutions through a collaboration with NetApp.

Fig. 2: At CadenceLive Silicon Valley, NVIDIA CEO Jensen Huang (r.) discussed accelerated computing and generative AI with Cadence CEO Anirudh Devgan. Source: Semiconductor Engineering

Quick links to more news:

Global
Markets and Money
In-Depth
Security
Education and Workforce
Product and Standards
Research
Quantum
Events
Further Reading

Global

After Taiwan’s recent 7.2 magnitude earthquake, TSMC reached more the 70% tool recovery in its fabs within the first 10 hours and full recovery by the end of the third day, according to this week’s earnings call. Some wafers in process were scrapped but the company expects the lost production to be recovered in the second quarter.  Also in the call, TSMC said they expect their “customers to share some of the higher cost” of the overseas fabs and higher electricity costs.

Advantest‘s regional headquarters in Taiwan donated $2.2 million New Taiwan dollars ($680,000 US) for aid to victims and reconstruction efforts related to the Taiwan earthquake that struck on April 3.

Japan’s exports grew by more than 7% YoY in March, driven by an 11.3% increase in shipments of electronics and semiconductor manufacturing equipment, much of it to China, according to NikkeiAsia.

China‘s IC output grew 40% in the first quarter, primarily driven by EVs and smartphones, according to the South China Morning Post.

In the U.S., the Biden Administration released a notice of funding opportunity of $50 million targeted at small businesses pursuing advances in metrology research and technology. Also, the U.S. Department of Energy announced a $33 million funding opportunity for smart manufacturing technologies.

Germany‘s Fraunhofer IIS launched its On-Board Processor (FOBP) for the German Space Agency’s Heinrich Hertz communication satellite. FOBP can be controlled and reprogrammed from Earth and will be used to investigate creation of hybrid communication networks.

Markets and Money

RISC-V startup Rivos raised more than $250 million in capital investments to tape out its first power-optimized chips for data analytics and generative AI applications.

Silvaco filed to go public on Nasdaq. The company also received a $5 million convertible note investment from Microchip.

Microchip acquired Neuronix AI Labs to provide AI-enabled FPGA solutions for large-scale, high-performance edge applications.

The advanced packaging market saw a modest 4% increase in revenues in Q4 2023 versus the previous quarter, with a projected decline of 13% QoQ in the first quarter of 2024, reports Yole. Overall, the market is expected to increase from $38 billion in 2023 to $69.5 billion in 2029 with a CAGR of 10.7%.

TSMC’s CoWoS total capacity will increase by 150% in 2024 due to demand for NVIDIA’s Blackwell Platform, reports TrendForce.

ASML saw a nearly 40% drop in new litho equipment sales QoQ in Q1 2024 and a 61% drop in net bookings as manufacturers reduced investments in new capital equipment during the recent semiconductor market slump.

Global PC shipments rose about 3% YoY in Q1 2024, and that same growth is expected for full year 2024, reports Counterpoint. Manufacturers are predicted to promote AI PCs as semiconductor companies prepare to launch SoCs featuring higher TOPS.

The GenAI smartphone market share is predicted to reach 11% by 2024 and 43% by 2027, reports Counterpoint. Samsung likely will lead in 2024, but Apple may overtake it in 2025.

The RF GaN market is expected to exceed $2 billion by 2029, fueled by the defense and telecom infrastructure sectors, reports Yole.

In-Depth

Semiconductor Engineering published its Manufacturing, Packaging & Materials newsletter this week. Top articles include:

• Electromigration Concerns Grow In Advanced Packages
• What Works Best For Chiplets
• Enabling Advanced Devices With Atomic Layer Processes

Plus, check out these new stories and tech talks:

• Architecting Chips For High-Performance Computing
• Future-Proofing Automotive V2X
• Secure Movement Of Data In Test
• Challenges With Chiplets and Power Delivery

Security

In security research:

• Seoul National University, Sandia National Laboratories, Texas A&M University, and Applied Materials demonstrated a memristor crossbar architecture for encryption and decryption.
• Robert Bosch, Forschungszentrum Julich, and Newcastle University investigated techniques for error detection and correction in in-memory computing.
• The University of Florida introduced an automated framework that can help identify security assets for a design at the register-transfer level (RTL).

DARPA conducted successful in-air tests of AI flying an F-16 autonomously versus a human-piloted F-16 in visual-range combat scenarios.

The National Security Agency’s Artificial Intelligence Security Center (NSA AISC) published joint guidance on deploying AI systems securely with the Cybersecurity and Infrastructure Security Agency (CISA), the Federal Bureau of Investigation (FBI), and international partners. CISA also issued other alerts.

Products and Standards

Samsung uncorked LPDDR5X DRAM built on a 12nm process that supports up to 10.7 Gbps and expands the single package capacity of mobile DRAM up to 32 GB.

Keysight revealed its next-generation RF circuit simulation tool that supports multi-physics co-design of circuit, electromagnetic, and electrothermal simulations across Cadence, Synopsys, and Keysight platforms.

Renesas released its FemtoClock family of ultra-low jitter clock generators and jitter attenuators with 8 and 12 outputs, enabling clock tree designs for high-speed interconnect systems in telecom and data center switches, routers, medical imaging, and more.

Movellus expanded its droop response solutions with Aeonic Generate AWM3, which responds to voltage droops within 1 to 2 clock cycles while providing enhanced observability for droop profiling and enabling fine-grained dynamic frequency scaling.

Efabless announced the second version of its Python-based open-source EDA software for construction of customizable flows using proprietary or open-source tools.

Faraday Technology licensed Arm’s Cortex-A720AE IP to use in the development of AI-enabled vehicle ASICs. Also, Untether AI teamed up with Arm to enable its inference acceleration technology to be implemented alongside the latest-generation Automotive Enhanced technology from Arm for ADAS and autonomous vehicle applications.

FOXESS used Infineon’s 1,200V CoolSiC MOSFETs and EiceDRIVER gate drivers for industrial energy storage applications, aiming to promote green energy.

Emotors adopted Siemens’ Simcenter solutions for NVH testing of next-gen automotive e-drives.

SiTime debuted a family of clock generators for AI datacenter applications with clock, oscillator, and resonator in an integrated chip.

JEDEC published the JESD79-5C DDR5 SDRAM standard, which includes a DRAM data integrity improvement called Per-Row Activation Counting (PRAC) that precisely counts DRAM activations on a wordline granularity and alerts the system to pause traffic and designate time for mitigation measures when an excessive number of activations are detected.

The LoRa Alliance launched its roadmap for the development of the LoRaWAN open standard for IoT communications, referring to long-range radio (LoRa) low-power wide-area networks (LPWANs).

Education and Workforce

Texas A&M introduced a new Master of Science program for microelectronics and semiconductors, which will begin in fall 2025.

The Cornell NanoScale Science and Technology Facility (CNF) is partnering with Tompkins Cortland Community College and Penn State to offer a free Microelectronics and Nanomanufacturing Certificate Program to veterans and their dependents.

Eindhoven University of Technology (TU/e) has more than 700 researchers and 25 research group focused on the chip industry, but the number is projected to grow significantly due to the Dutch government’s recent investment.

Research

Intel announced a large-scale neuromorphic system based on its Loihi 2 processor. Initially deployed at Sandia National Laboratories, it aims to support research for future brain-inspired AI. Intel is also collaborating with Seekr on next-gen LLM and foundation models.

Los Alamos National Lab, HPE, and NVIDIA collaborated on the design and installation of Venado, the Lab’s new supercomputer. “Venado adds to our cutting-edge supercomputing that advances national security and basic research, and it will accelerate how we integrate artificial intelligence into meeting those challenges,” said Thom Mason, director of Los Alamos National Laboratory in a release.

Penn State is partnering with Morgan Advanced Materials on a five-year, multi-million-dollar research project to advance silicon carbide (SiC) technology. Morgan will become a founding member of the Penn State Silicon Carbide Innovation Alliance. Also, Coherent secured CHIPS Act funding of $15 million for research into high-voltage, high-power silicon carbide and single-crystal diamond semiconductors.

Oak Ridge National Laboratory (ORNL) researchers found a more efficient way to extract lithium from waste liquids leached from mining sites, oil fields, and used batteries.

Quantum

Quantinuum said it reached an inherent 99.9% 2-qubit gate fidelity in its commercial quantum computer, a point at which quantum error correction protocols can be used to greatly reduce error rates.

D-Wave Quantum uncorked a fast-anneal feature to speed up computations on its quantum processing units, which reduces the impact of external disturbances.

MIT researchers outlined a new conceptual model for a quantum computer that aims to make writing code for them easier.

SLAC National Accelerator Laboratory, Stanford University, Max Planck Institute of Quantum Optics, Ludwig-Maximilians-Universitat Munich, and Instituto de Ciencia de Materiales de Madrid researchers proposed a method that harnesses the structure of light to tweak the properties of quantum materials.

Events

Find upcoming chip industry events here, including:

Upcoming webinars are here.

Further Reading

Read the latest special reports and top stories, or check out the latest newsletters:

Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials
Automotive, Security and Pervasive Computing

The post Chip Industry Week In Review appeared first on Semiconductor Engineering.

Abstract:

“Full-chip curvilinear inverse lithography technology (ILT) requires mask writers to write full reticle curvilinear mask patterns in a reasonable write time. We jointly study and present the benefits of a full-chip, curvilinear, stitchless ILT with mask-wafer co-optimization (MWCO) for variable-shaped beam (VSB) mask writers and validate its benefits on mask and wafer at Micron Technology. The full-chip ILT technology employed, first demonstrated in a paper presented at the 2019 SPIE Photomask Technology Conference, produces curvilinear ILT mask patterns without stitching errors, and with process windows enlarged by over 100% compared to the OPC process of record, while the mask was written by multibeam mask writer. At the 2020 SPIE Advanced Lithography Conference, a method was introduced in which MWCO is performed during ILT optimization. This approach enables curvilinear ILT for 193i masks to be written on VSB mask writers within a practical, 12-h time frame, while also producing the largest process windows. We first review MWCO technology, then curvilinear ILT mask patterns written by VSB mask writer, and then show the corresponding 193i process wafer prints. Evaluations of mask write times and mask quality in terms of critical dimension uniformity and process windows are also presented.”

Find the technical paper here. Published February 2024.

Pang, Linyong, Sha Lu, Ezequiel Vidal Russell, Yang Lu, Michael Lee, Jennefir Digaum, Ming-Chuan Yang et al. “Make the impossible possible: use variable-shaped beam mask writers and curvilinear full-chip inverse lithography technology for 193i contacts/vias with mask-wafer co-optimization.” Journal of Micro/Nanopatterning, Materials, and Metrology 23, no. 1 (2024): 011207-011207.

Author Affiliations: D2S Inc. and Micron Technology Inc.

The post Make The Impossible Possible: Use Variable-Shaped Beam Mask Writers And Curvilinear Full-Chip Inverse Lithography Technology For 193i Contacts/Vias With Mask-Wafer Co-Optimization appeared first on Semiconductor Engineering.