JEDEC and the Open Compute Project rolled out a new set of guidelines for standardizing chiplet characterization details, such as thermal properties, physical and mechanical requirements, and behavior specs. Those details have been a sticking point for commercial chiplets, because without them it’s not possible to choose the best chiplet for a particular application or workload. The guidelines are a prerequisite for a multi-vendor chiplet marketplace.

AMD, Broadcom, Cisco, Google, HPE, Intel, Meta, and Microsoft proposed a new high-speed, low-latency interconnect specification, Ultra Accelerator Link (UALink), between accelerators and switches in AI computing pods. The 1.0 specification will enable the connection of up to 1,024 accelerators within a pod and allow for direct loads and stores between the memory attached to accelerators.

Arm debuted a range of new CPUs, including the Cortex-X925 for on-device generative AI, and the Cortex-A725 with improved efficiency for AI and mobile gaming. It also announced the Immortalis-G925 GPU for flagship smartphones, and the Mali-G725/625 GPUs for consumer devices. Additionally, Arm announced Compute Subsystems (CSS) for Client to provide foundational computing elements for AI smartphone and PC SoCs, and it introduced KleidiAI, a set of compute kernels for developers of AI frameworks. The Armv9-A architecture also added support for the Scalable Matrix Extension to accelerate AI workloads.

TSMC said its 2nm process is on target to begin mass production in 2025. Meanwhile, Samsung is expected to release its 1nm plan next month, targeting mass production for 2026 — a year ahead of schedule, reports Business Korea.

CHIPs for America and NATCAST released a 2024 roadmap for the U.S. National Semiconductor Technology Center (NSTC), identifying priorities for facilities, research, workforce development, and membership.

China is investing CNY 344 billion (~$47.5 billion) into the third phase of its National Integrated Circuit Industry Investment Fund, also known as the Big Fund, to support its semiconductor sector and supply chain, according to numerous reports.

Malaysia plans to invest $5.3 billion in seed capital and support for semiconductor manufacturing in an effort to attract more than $100 billion in foreign investments, reports Reuters. Prime Minister Anwar Ibrahim announced the effort to create at least 10 companies focused on IC design, advanced packaging, and equipment manufacturing.

imec demonstrated a die-to-wafer hybrid bonding flow for Cu-Cu and SiCN-SiCN at pitches down to 2µm at the IEEE’s ECTC conference. This breakthrough could enable die and wafer-level optical interconnects.

The chip industry is racing to develop glass for advanced packaging, setting the stage for one of the biggest shifts in chip materials in decades — and one that will introduce a broad new set of challenges that will take years to fully resolve.

Quick links to more news:

In-Depth
Global
Product News
Markets and Money
Security
Research and Training
Quantum
Events and Further Reading

In-Depth

Semiconductor Engineering published its Systems & Design newsletter featuring these top stories:

• RISC-V Heralds New Era Of Cooperation
• AI For Data Management
• Trouble Ahead For IC Verification

Global

STMicroelectronics is building a fully integrated SiC facility in Catania, Italy.  The high-volume 200mm facility is projected to cost over $5 billion.

Siliconware Precision Industries Co. Ltd.(SPIL) broke ground on an RM 6 billion (~$1.3 billion) advanced packaging and testing facility in Malaysia. Also, Google will invest $2 billion in Malaysia for its first data center, and a Google Cloud hub to meet growing demand for cloud services and AI literacy programs, reports AP.

In an SEC filing, Applied Materials received additional subpoenas from the U.S. Department of Commerce’s (DoC) Bureau of Industry and Security related to shipments of advanced semiconductor equipment to China. This comes on the heels of similar subpoenas issued last year.

A Chinese contractor working for SK hynix was arrested in South Korea and is being charged with funneling more than 3,000 copies of a paper on solving process failure issues to Huawei, reports South Korea’s Union News.

VSORA, CEA-Grenoble, and Valeo were awarded $7 million from the French government to build low-latency, low-power AI inference co-processors for autonomous driving and other applications.

In the U.S., the National Highway Traffic Safety Administration (NHTSA) is investigating unexpected driving behaviors of vehicles equipped with Waymo‘s 5th Generation automated driving system (ADS), with details of nine new incidents on top of the first 22.

Product News

ASE introduced powerSIP, a power delivery platform designed to reduce signal and transmission loss while addressing current density challenges.

Infineon announced a roadmap for energy-efficient power supply units based on Si, SiC, and GaN to address the energy needs of AI data centers, featuring new 8 kW and 12 kW PSUs, in addition to the 3 kW and 3.3 kW units available today. The company also released its CoolSiC MOSFET 400 V family, specially developed for use in the AC/DC stage of AI servers, complementing the PSU roadmap.

Fig. 1: Infineon’s 8kW PSU. Source: Infineon

Infineon also introduced two new generations of high voltage (HV) and medium voltage (MV) CoolGaN TM devices, enabling customers to use GaN in voltage classes from 40 V to 700 V. The devices are built using Infineon’s 8-inch foundry processes.

Ansys launched Ansys Access on Microsoft Azure to provide pre-configured simulation products optimized for HPC on Azure infrastructure.

Foxconn Industrial Internet used Keysight Technology’s Open RAN Studio solution to certify an outdoor Open Radio Unit (O-RU).

Andes Technology announced an SoC and development board for the development and porting of large RISC-V applications.

MediaTek uncorked a pair of mobile chipsets built on a 4nm process that use an octa-core CPU consisting of 4X Arm Cortex-A78 cores operating at up to 2.5GHz paired with 4X Arm Cortex-A55 cores.

The NVIDIA H200 Blackwell platform is expected to begin shipping in Q3 of 2024 and will be available to data centers by Q4, according to TrendForce.

A room-temperature direct fusion hybrid bonding system from Be Semiconductor has shipped to the NHanced advanced packaging facility in North Carolina. The new system offers faster throughput for copper interconnects with submicron pad sizes, greater accuracy and reduced warpage.

Markets and Money

Frore Systems raised $80 million for its solid-state active cooling module, which removes heat from the top of a chip without fans. The device in systems ranging from notebooks and network edge gateways to data centers.

Axus Technology received $12.5 million in capital equity funding to make its chemical mechanical planarization (CMP) equipment for semiconductor wafer polishing, thinning, and cleaning, including of silicon carbide (SiC) wafers.

Elon Musk’s xAI announced a series B funding round of $6 billion.

Micron was ordered to pay $445 million in damages to Netlist for patent infringement of the company’s DDR4 memory module technology between 2021 and 2024.

Global revenue from AI semiconductors is predicted to total $71 billion in 2024, up 33% from 2023, according to Gartner. In 2025, it is expected to jump to $91.9 billion. The value of AI accelerators used in servers is expected to total $21 billion in 2024 and reach $33 billion by 2028.

NAND flash revenue was $14.71 billion in Q1 2024, an increase of 28.1%, according to TrendForce.

The optical transceiver market dipped from $11 billion in 2022 to $10.9 billion in 2023, but it is predicted to reach $22.4 billion by 2029, driven by AI, 800G applications, and the transition to 200G/lane ecosystem technologies, reports Yole.

Yole also found that ultra-wideband technical choices and packaging types used by NXP, Apple, and Qorvo vary considerably, ranging from 7nm to 90nm, with both CMOS and finFET transistors.

The global market share of GenAI-capable smartphones increased to 6% in Q1 2024 from 1.3% in the previous quarter, reports Counterpoint. The premium segment accounted for over 70% of sales with Samsung on top and contributing 58%. Meanwhile, global foldable smartphone shipments were up 49% YoY in Q1 2024, led by Huawei, HONOR, and Motorola.

Security

The National Science Foundation awarded Worcester Polytechnic Institute researcher Shahin Tajik almost $0.6 million to develop new technologies to address hardware security vulnerabilities.

The Hyperform consortium was formed to develop European sovereignty in post-quantum cryptography, funded by the French government and EU credits. Members include IDEMIA Secure Transactions, CEA Leti, and the French cybersecurity agency (ANSSI).

In security research:

• University of California Davis and University of Arizona researchers proposed a framework leveraging generative pre-trained transformer (GPT) models to automate the obfuscation process.
• Columbia University and Intel researchers presented a secure digital low dropout regulator that integrates an attack detector and a detection-driven protection scheme to mitigate correlation power analysis.
• Pohang University of Science and Technology (POSTECH) researchers analyzed threshold switch devices and their performance in hardware security.

The U.S. Defense Advanced Research Projects Agency (DARPA) seeks proposals for its AI Quantified program to develop technology to help deploy generative AI safely and effectively across the Department of Defense (DoD) and society.

Vanderbilt University and Oak Ridge National Laboratory (ORNL) partnered to develop dependable AI for national security applications.

The Cybersecurity and Infrastructure Security Agency (CISA) issued a number of alerts/advisories.

Research and Training

New York continues to amp up their semiconductor offerings. NY CREATES and Raytheon unveiled a semiconductor workforce training program. And Syracuse  University is hosting a free virtual course focused on the semiconductor industry this summer.

In research news:

• A team of researchers at MIT and other universities found that extreme temperatures up to 500°C did not significantly degrade GaN materials or contacts.
• University of Cambridge researchers developed adaptive and eco-friendly sensors that can be directly and imperceptibly printed onto biological surfaces, such as a finger or flower petal.
• Researchers at Rice University and Hanyang University developed an elastic material that moves like skin and can adjust its dielectric frequency to stabilize RF communications and counter disruptive frequency shifts that interfere with electronics when a substrate is twisted or stretched, with potential for stretchable wearable electronic devices.

The National Science Foundation (NSF) awarded $36 million to three projects chosen for their potential to revolutionize computing. The University of Texas at Austin-led project aims to create a next-gen open-source intelligent and adaptive OS. The Harvard University-led project targets sustainable computing. The University of Massachusetts Amherst-led project will develop computational decarbonization.

Quantum

Singapore will invest close to S$300 million (~$222 million) into its National Quantum Strategy to support the development and deployment of quantum technologies, including an initiative to design and build a quantum processor within the country.

Several quantum partnerships were announced:

• Riverlane and Alice & Bob will integrate Riverlane’s quantum error correction stack within Alice & Bob’s larger quantum computing system based on cat qubit technology.
• New York University and the University of Copenhagen will collaborate to explore the viability of hybrid superconductor-semiconductor quantum materials for the production of quantum chips and integration with CMOS processes.
• NXP, eleQtron, and ParityQC showed off a full-stack, ion-trap based quantum computer demonstrator for Germany’s DLR Quantum Computing Initiative.
• Photonic says it demonstrated distributed entanglement between quantum modules using optically-linked silicon spin qubits with a native telecom networking interface as part of a quantum internet effort with Microsoft.
• Classiq and HPE say they developed a rapid method for solving large-scale combinatorial optimization problems by combining quantum and classical HPC approaches.

Events and Further Reading

Find upcoming chip industry events here, including:

Upcoming webinars are here, including integrated SLM analytics solution, prototyping and validation of perception sensor systems, and improving PCB designs for performance and reliability.

Semiconductor Engineering’s latest newsletters:

Automotive, Security and Pervasive Computing
Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials

The post Chip Industry Week In Review appeared first on Semiconductor Engineering.

DNA assembly of 3D nanomaterials

Scientists from Brookhaven National Laboratory, Columbia University, and Stony Brook University developed a method that uses DNA to instruct molecules to organize themselves into targeted 3D patterns and produce a wide variety of designed metallic and semiconductor 3D nanostructures.

“We have been using DNA to program nanoscale materials for more than a decade,” said corresponding author Oleg Gang, a professor of chemical engineering and of applied physics and materials science at Columbia Engineering, in a release. “Now, by building on previous achievements, we have developed a method for converting these DNA-based structures into many types of functional inorganic 3D nano-architectures, and this opens tremendous opportunities for 3D nanoscale manufacturing.”

Researchers program strands of DNA to “direct” the self-assembly process towards molecular arrangements that give rise to properties such as electrical conductivity, photosensitivity, and magnetism, which can then be scaled up to functional materials.

The team used the method to grow silica on a DNA lattice, which helped to create a robust structure. They then used vapor-phase infiltration and liquid-phase infiltration, which bonds a precursor chemical in vapor or liquid form to a nanoscale lattice, to produce a variety of 3D metallic structures.

Scientists used a new, universal method to create a variety of 3D metallic and semiconductor nanostructures, including this structure revealed by an electron microscope. The scale bar represents one micrometer. The superimposed graphics convey that the researchers combined multiple techniques to layer silicon dioxide, then alumina-doped zinc oxide, and finally platinum on top of a DNA “scaffolding.” This complex structure represents new possibilities for advanced manufacturing at small scales. (Credit: Brookhaven National Laboratory)

“Stacking these techniques showed much more depth of control than has ever been accomplished before,” said Aaron Michelson, a postdoctoral researcher at Brookhaven’s Center for Functional Nanomaterials, in a release. “Whatever vapors are available as precursors for vapor-phase infiltration can be coupled with various metal salts compatible with liquid-phase infiltration to create more complex structures. For example, we were able to combine platinum, aluminum, and zinc on top of one nanostructure.”

They were also able to add on semiconducting metal oxides, such as zinc oxide, to an insulating nanostructure, providing it with electrical conductivity and photoluminescent properties. [1]

Mott insulator transistor

Researchers from the University of Nebraska-Lincoln, Brookhaven National Laboratory, University of the Basque Country, and NYU Shanghai propose a way to make transistors out of Mott insulators.

The researchers were able to direct the Mott transition from insulator to metal and back again by topping a Mott insulator with a gate insulator made of a ferroelectric material and using a voltage to flip the ferroelectric material’s polarization. A third layer beneath the Mott channel that allows charges to migrate from the Mott down to it improved control over the insulator-metal transition with an on-off ratio of 385.

Additionally, the researchers claim that the Mott-ferroelectric pairing is more energy-efficient than other non-volatile but magnetism-based memory, including MRAM.

“We can have very high-performance devices, retaining many manufacturing processes of conventional semiconductors and overcoming some fundamental limitations of them,” said Xia Hong, professor of physics at the University of Nebraska-Lincoln, in a release. “I think it’s ready. It’s really competitive with other non-volatile memory technologies.” [2]

Faster wireless data speeds

Researchers from Osaka University and IMRA America suggest a way to increase wireless data transmission speeds by reducing the noise in the system using lasers.

Future 6G transmitters and receivers are expected to use the sub-terahertz band, which extends from 100 GHz to 300 GHz, using an approach called “multi-level signal modulation” to further increase the data transmission rate. However, this approach is highly sensitive to noise at the upper end of the frequency range.

“This problem has limited 300-GHz communications so far,” said Keisuke Maekawa of Osaka University in a statement. “However, we found that at high frequencies, a signal generator based on a photonic device had much less phase noise than a conventional electrical signal generator.”

The team used a stimulated Brillouin scattering laser, which employs interactions between sound and light waves, to generate a precise signal. They then set up a 300 GHz-band wireless communication system that employs the laser-based signal generator in both the transmitter and receiver. The system also used on-line digital signal processing (DSP) to demodulate the signals in the receiver and increase the data rate.

“Our team achieved a single-channel transmission rate of 240 gigabits per second,” said Tadao Nagatsuma, a professor at Osaka University, in a release. “This is the highest transmission rate obtained so far in the world using on-line DSP.” The researchers expect that with multiplexing techniques and more sensitive receivers, the data rate can be increased to 1 terabit per second. [3]

References

[1] Aaron Michelson et al., Three-dimensional nanoscale metal, metal oxide, and semiconductor frameworks through DNA-programmable assembly and templating. Sci. Adv. 10, eadl0604 (2024). https://doi.org/10.1126/sciadv.adl0604

[2] Hao, Y., Chen, X., Zhang, L. et al. Record high room temperature resistance switching in ferroelectric-gated Mott transistors unlocked by interfacial charge engineering. Nat Commun 14, 8247 (2023). https://doi.org/10.1038/s41467-023-44036-x

[3] Keisuke Maekawa, Tomoya Nakashita, Toki Yoshioka, Takashi Hori, Antoine Rolland, Tadao Nagatsuma, Single-channel 240-Gbit/s sub-THz wireless communications using ultra-low phase noise receiver, IEICE Electronics Express, Article ID 20.20230584, Advance online publication December 25, 2023, Online ISSN 1349-2543, https://doi.org/10.1587/elex.20.20230584

The post Research Bits: Feb. 19 appeared first on Semiconductor Engineering.