EUV mirror interference lithography

Researchers from the Paul Scherrer Institute developed an EUV lithography technique that can produce conductive tracks with a separation of just five nanometers by exposing the sample indirectly rather than directly.

Called EUV mirror interference lithography (MIL), the technique uses two mutually coherent beams that are reflected onto the wafer by two identical mirrors. The beams then create an interference pattern whose period depends on both the angle of incidence and the wavelength of the light. In addition to the 5nm resolution, the conductive tracks were found to have high contrast and sharp edges.

“Our results show that EUV lithography can produce extremely high resolutions, indicating that there are no fundamental limitations yet. This is really exciting since it extends the horizon of what we deem as possible and can also open up new avenues for research in the field of EUV lithography and photoresist materials,” said Dimitrios Kazazis of the Laboratory of X-ray Nanoscience and Technologies at PSI in a statement.

The method is currently too slow for industrial chip production and can produce only simple and periodic structures. However, the team sees it as a resource for early development of new photoresists and plans to continue research to improve its performance and capabilities. [1]

Artificial sapphire dielectrics

Researchers from Shanghai Institute of Microsystem and Information Technology created artificial sapphire dielectric wafers made of single-crystalline aluminum oxide (Al₂O₃).

“The aluminum oxide we created is essentially artificial sapphire, identical to natural sapphire in terms of crystal structure, dielectric properties and insulation characteristics,” said Tian Zi’ao, a researcher at SIMIT, in a release.

“By using intercalation oxidation technology on single-crystal aluminum, we were able to produce this single-crystal aluminum oxide dielectric material,” added Di Zengfeng, a researcher at SIMIT, in a release. “Unlike traditional amorphous dielectric materials, our crystalline sapphire can achieve exceptionally low leakage at just one-nanometer level.”

The researchers hope the improved dielectric properties could lead to more power-efficient devices. [2]

Accelerating computation on sparse data sets

Researchers from Lehigh University and Lawrence Berkeley National Laboratory developed specialized hardware that enables faster computation on data sets that have a high number of zero values, frequent in the fields of bioinformatics and physical sciences. The hardware is portable and can be integrated into general-purpose multi-core computers.

“The accelerating sparse accumulation (ASA) architecture includes a hardware buffer, a hardware cache, and a hardware adder. It takes two sparse matrices, performs a matrix multiplication, and outputs a sparse matrix. The ASA only uses non-zero data when it performs this operation, which makes the architecture more efficient. The hardware buffer and the cache allow the computer processor to easily manage the flow of data; the hardware adder allows the processor to quickly generate values to fill up the empty matrices,” explained Berkely Lab’s Ingrid Ockert in a press release. “Once these values are calculated, the ASA system produces an output. This operation is a building block that the researcher can then use in other functions. For instance, researchers could use these outputs to generate graphs or they could process these outputs through other algorithms such as a Sparse General Matrix-Matrix Multiplication (SpGEMM) algorithm.”

The ASA architecture could accelerate a variety of algorithms. Microbiome research is presented as an example, where it could be used to run metagenomic assembly and similarity clustering algorithms such as Markov Cluster Algorithms that quickly characterize the genetic markers of all of the organisms in a soil sample. [3]

References

[1] I. Giannopoulos, I. Mochi, M. Vockenhuber, Y. Ekinci & D. Kazazis. Extreme ultraviolet lithography reaches 5 nm resolution. Nanoscale, 12.08.2024 https://doi.org/10.1039/D4NR01332H

[2] Zeng, D., Zhang, Z., Xue, Z. et al. Single-crystalline metal-oxide dielectrics for top-gate 2D transistors. Nature (2024). https://doi.org/10.1038/s41586-024-07786-2

[3] Chao Zhang, Maximilian Bremer, Cy Chan, John M Shalf, and Xiaochen Guo. ASA: Accelerating Sparse Accumulation in Column-wise SpGEMM. ACM Transactions on Architecture and Code Optimization (TACO) Volume 19, Issue 4, Article No.: 49, Pages 1-24 https://doi.org/10.1145/3543068

The post Research Bits: Aug. 20 appeared first on Semiconductor Engineering.

Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML.

Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government disagreements over how to fund chip R&D, according to Bloomberg.

SEMI published a position paper this week cautioning the European Union against imposing additional export controls to allow companies, encouraging them to  be “as free as possible in their investment decisions to avoid losing their agility and relevance across global markets.” SEMI’s recommendations on outbound investments are in response to the European Economic Security Strategy and emphasize the need for a transparent and predictable regulatory framework.

The U.S. may restrict China’s access to HBM chips and the equipment needed to make them, reports Bloomberg. Today those chips are manufactured by two Korean-based companies, Samsung and SK hynix, but U.S.-based Micron expects to begin shipping 12-high stacks of HBM3E in 2025, and is currently working on HBM4.

Synopsys executive chair and founder Dr. Aart de Geus was named the winner of the Semiconductor Industry Association’s Robert N. Noyce Award. De Geus was selected due to his contributions to EDA technology over a career spanning more than four decades.

The top three foundries plan to implement high-NA EUV lithography as early as 2025 for the 18 angstrom generation, but the replacement of single exposure high-NA (0.55) over double patterning with standard EUV (NA = 0.33) depends on whether it provides better results at a reasonable cost per wafer.

Quick links to more news:

Global
In-Depth
Market Reports and Earnings
Education and Training
Security
Product News
Research
Events and Further Reading

Global

Belgium-based Imec released part 2 of its chiplets series, addressing testing strategies and standardization efforts, as well as guidelines and research “towards efficient ESD protection strategies for advanced 3D systems-on-chip.”

Also in Belgium, BelGan, maker of GaN chips, filed for bankruptcy according to the Brussels Times.

TSMC‘s Dresden, Germany, plant will break ground this month.

The UK will dole out more than £100 million (~US $128 million) in funding to develop five new quantum research hubs in Glasgow, Edinburgh, Birmingham, Oxford, and London.

MassPhoton is opening Hong Kong‘s first ultra-high vacuum GaN epitaxial wafer pilot line and will establish a GaN research center.

Infineon completed the sale of its manufacturing sites in the Philippines and South Korea to ASE.

Israel-based RAAAM Memory Technologies received a €5.25 million grant from the European Innovation Council (EIC) to support the development and commercialization of its innovative memory solutions. This funding will enable RAAAM to advance its research in high-performance and energy-efficient memory technologies, accelerating their integration into various applications and markets.

In-Depth

Semiconductor Engineering published its Automotive, Security and Pervasive Computing newsletter this week, featuring these top stories and video:

• Chip Security Now Depends On Widening Supply Chain
• Defining Chip Threat Models To Determining Security Risks
• Post-Quantum Computing Threatens Fundamental Transport Protocols

And:

• Where Power Savings Really Count
• Making Electronics More Efficient (video)

Market Reports and Earnings

The semiconductor equipment industry is on a positive trajectory in 2024, with moderate revenue growth observed in Q2 after a subdued Q1, according to a new report from Yole Group. Wafer Fab Equipment revenue is projected to grow by 1.3% year-on-year, despite a 12% drop in Q1. Test equipment lead times are normalizing, improving order conditions. Key areas driving growth include memory and logic capital expenditures and high-bandwidth memory demand.

Worldwide silicon wafer shipments increased by 7% in Q2 2024, according to SEMI‘s latest report. This growth is attributed to robust demand from multiple semiconductor sectors, driven by advancements in AI, 5G, and automotive technologies.

The RF GaN market is projected to grow to US $2 billion by 2029, a 10% CAGR, according to Yole Group.

Counterpoint released their Q2 smartphone top 10 report.

Renesas completed their acquisition of EDA firm Altium, best known for its EDA platform and freeware CircuitMaker package.

It’s earnings season and here are recently released financials in the chip industry:

AMD  Advantest   Amkor   Ansys  Arteris   Arm   ASE   ASM   ASML
Cadence  IBM   Intel   Lam Research   Lattice   Nordson   NXP   Onsemi 
Qualcomm   Rambus  Samsung    SK Hynix   STMicro   Teradyne    TI  
Tower  TSMC    UMC  Western Digital

Industry stock price impacts are here.

Education and Training

Rochester Institute of Technology is leading a new pilot program to prepare community college students in areas such as cleanroom operations, new materials, simulation, and testing processes, with the intent of eventual transfer into RIT’s microelectronic engineering program.

Purdue University inked a deal with three research institutions — University of Piraeus, Technical University of Crete, and King’s College London —to develop joint research programs for semiconductors, AI and other critical technology fields.

The European Chips Skills Academy formed the Educational Leaders Board to help bridge the talent gap in Europe’s microelectronics sector.  The Board includes representatives from universities, vocational training providers, educators and research institutions who collaborate on strategic initiatives to strengthen university networks and build academic expertise through ECSA training programs.

Security

The Cybersecurity and Infrastructure Security Agency (CISA) is encouraging Apple users to review and apply this week’s recent security updates.

Microsoft Azure experienced a nearly 10 hour DDoS attack this week, leading to global service disruption for many customers.  “While the initial trigger event was a Distributed Denial-of-Service (DDoS) attack, which activated our DDoS protection mechanisms, initial investigations suggest that an error in the implementation of our defenses amplified the impact of the attack rather than mitigating it,” stated Microsoft in a release.

NIST published:

• “Recommendations For Increasing U.S. Participation and Leadership in Standards Development,” a report outlining cybersecurity recommendations and mitigation strategies.
• Final guidance documents and software to help improve the “safety, security and trustworthiness of AI systems.”
• Cloud Computing Forensic Reference Architecture guide.

Delta Air Lines plans to seek damages after losing $500 million in lost revenue due to security company CrowdStrike‘s software update debacle.  And shareholders are also angry.

Recent security research:

• Physically Secure Logic Locking With Nanomagnet Logic (UT Dallas)
• WBP: Training-time Backdoor Attacks through HW-based Weight Bit Poisoning (UCF)
• S-Tune: SOT-MTJ Manufacturing Parameters Tuning for Secure Next Generation of Computing ( U. of Arizona, UCF)
• Diffie Hellman Picture Show: Key Exchange Stories from Commercial VoWiFi Deployments (CISPA, SBA Research, U. of Vienna)

Product News

Lam Research introduced a new version of its cryogenic etch technology designed to enhance the manufacturing of 3D NAND for AI applications. This technology allows for the precise etching of high aspect ratio features, crucial for creating 1,000-layer 3D NAND.

Fig.1: 3D NAND etch. Source: Lam Research

Alphawave Semi launched its Universal Chiplet Interconnect Express Die-to-Die IP. The subsystem offers 8 Tbps/mm bandwidth density and supports operation at 24 Gbps for D2D connectivity.

Infineon introduced a new MCU series for industrial and consumer motor controls, as well as power conversion system applications. The company also unveiled its new GoolGaN Drive product family of integrated single switches and half-bridges with integrated drivers.

Rambus released its DDR5 Client Clock Driver for next-gen, high-performance desktops and notebooks. The chips include Gen1 to Gen4 RCDs, power management ICs, Serial Presence Detect Hubs, and temperature sensors for leading-edge servers.

SK hynix introduced its new GDDR7 graphics DRAM. The product has an operating speed of 32Gbps, can process 1.5TB of data per second and has a 50% power efficiency improvement compared to the previous generation.

Intel launched its new Lunar Lake Ultra processors. The long awaited chips will be included in more than 80 laptop designs and has more than 40 NPU tera operations per second as well as over 60 GPU TOPS delivering more than 100 platform TOPS.

Brewer Science achieved recertification as a Certified B Corporation, reaffirming its commitment to sustainable and ethical business practices.

Panasonic adopted Siemens’ Teamcenter X cloud product lifecycle management solution, citing Teamcenter X’s Mendix low-code platform, improved operational efficiency and flexibility for its choice.

Keysight validated its 5G NR FR1 1024-QAM demodulation test cases for the first time. The 5G NR radio access technology supports eMBB and was validated on the 3GPP TS 38.521-4 test specification.

Research

In a 47-page deep-dive report, the Center for Security and Emerging Technology delved into all of the scientific breakthroughs from 1980 to present that brought EUV lithography to commercialization, including lessons learned for the next emerging technologies.

Researchers at the Paul Scherrer Institute developed a high-performance X-ray tomography technique using burst ptychography, achieving a resolution of 4nm. This method allows for non-destructive imaging of integrated circuits, providing detailed views of nanostructures in materials like silicon and metals.

MIT signed a four-year agreement with the Novo Nordisk Foundation Quantum Computing Programme at University of Copenhagen, focused on accelerating quantum computing hardware research.

MIT’s Research Laboratory of Electronics (RLE) developed a mechanically flexible wafer-scale integrated photonics fabrication platform. This enables the creation of flexible photonic circuits that maintain high performance while being bendable and stretchable. It offers significant potential for integrating photonic circuits into various flexible substrate applications in wearable technology, medical devices, and flexible electronics.

The Naval Research Lab identified a new class of semiconductor nanocrystals with bright ground-state excitons, emphasizing an important advancement in optoelectronics.

Researchers from National University of Singapore developed a novel method, known as tension-driven CHARM3D,  to fabricate 3D self-healing circuits, enabling the 3D printing of free-standing metallic structures without the need for support materials and external pressure.

Find more research in our Technical Papers library.

Events and Further Reading

Find upcoming chip industry events here, including:

Upcoming webinars are here, including topics such as quantum safe cryptography, analytics for high-volume manufacturing, and mastering EMC simulations for electronic design.

Find Semiconductor Engineering’s latest newsletters here:

Automotive, Security and Pervasive Computing
Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials

The post Chip Industry Week in Review appeared first on Semiconductor Engineering.

A new technical paper titled “An Evaluation of Continual Learning for Advanced Node Semiconductor Defect Inspection” was published by Imec and SCREEN SPE Germany.

Abstract

“Deep learning-based semiconductor defect inspection has gained traction in recent years, offering a powerful and versatile approach that provides high accuracy, adaptability, and efficiency in detecting and classifying nano-scale defects. However, semiconductor manufacturing processes are continually evolving, leading to the emergence of new types of defects over time. This presents a significant challenge for conventional supervised defect detectors, as they may suffer from catastrophic forgetting when trained on new defect datasets, potentially compromising performance on previously learned tasks. An alternative approach involves the constant storage of previously trained datasets alongside pre-trained model versions, which can be utilized for (re-)training from scratch or fine-tuning whenever encountering a new defect dataset. However, adhering to such a storage template is impractical in terms of size, particularly when considering High-Volume Manufacturing (HVM). Additionally, semiconductor defect datasets, especially those encompassing stochastic defects, are often limited and expensive to obtain, thus lacking sufficient representation of the entire universal set of defectivity. This work introduces a task-agnostic, meta-learning approach aimed at addressing this challenge, which enables the incremental addition of new defect classes and scales to create a more robust and generalized model for semiconductor defect inspection. We have benchmarked our approach using real resist-wafer SEM (Scanning Electron Microscopy) datasets for two process steps, ADI and AEI, demonstrating its superior performance compared to conventional supervised training methods.”

Find the technical paper here.  Published July 2024 (preprint).

Prasad, Amit, Bappaditya Dey, Victor Blanco, and Sandip Halder. “An Evaluation of Continual Learning for Advanced Node Semiconductor Defect Inspection.” arXiv preprint arXiv:2407.12724 (2024).

The post Classification and Localization of Semiconductor Defect Classes in Aggressive Pitches (imec, Screen) appeared first on Semiconductor Engineering.

Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML.

Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government disagreements over how to fund chip R&D, according to Bloomberg.

SEMI published a position paper this week cautioning the European Union against imposing additional export controls to allow companies, encouraging them to  be “as free as possible in their investment decisions to avoid losing their agility and relevance across global markets.” SEMI’s recommendations on outbound investments are in response to the European Economic Security Strategy and emphasize the need for a transparent and predictable regulatory framework.

The U.S. may restrict China’s access to HBM chips and the equipment needed to make them, reports Bloomberg. Today those chips are manufactured by two Korean-based companies, Samsung and SK hynix, but U.S.-based Micron expects to begin shipping 12-high stacks of HBM3E in 2025, and is currently working on HBM4.

Synopsys executive chair and founder Dr. Aart de Geus was named the winner of the Semiconductor Industry Association’s Robert N. Noyce Award. De Geus was selected due to his contributions to EDA technology over a career spanning more than four decades.

The top three foundries plan to implement high-NA EUV lithography as early as 2025 for the 18 angstrom generation, but the replacement of single exposure high-NA (0.55) over double patterning with standard EUV (NA = 0.33) depends on whether it provides better results at a reasonable cost per wafer.

Quick links to more news:

Global
In-Depth
Market Reports and Earnings
Education and Training
Security
Product News
Research
Events and Further Reading

Global

Belgium-based Imec released part 2 of its chiplets series, addressing testing strategies and standardization efforts, as well as guidelines and research “towards efficient ESD protection strategies for advanced 3D systems-on-chip.”

Also in Belgium, BelGan, maker of GaN chips, filed for bankruptcy according to the Brussels Times.

TSMC‘s Dresden, Germany, plant will break ground this month.

The UK will dole out more than £100 million (~US $128 million) in funding to develop five new quantum research hubs in Glasgow, Edinburgh, Birmingham, Oxford, and London.

MassPhoton is opening Hong Kong‘s first ultra-high vacuum GaN epitaxial wafer pilot line and will establish a GaN research center.

Infineon completed the sale of its manufacturing sites in the Philippines and South Korea to ASE.

Israel-based RAAAM Memory Technologies received a €5.25 million grant from the European Innovation Council (EIC) to support the development and commercialization of its innovative memory solutions. This funding will enable RAAAM to advance its research in high-performance and energy-efficient memory technologies, accelerating their integration into various applications and markets.

In-Depth

Semiconductor Engineering published its Automotive, Security and Pervasive Computing newsletter this week, featuring these top stories and video:

• Chip Security Now Depends On Widening Supply Chain
• Defining Chip Threat Models To Determining Security Risks
• Post-Quantum Computing Threatens Fundamental Transport Protocols

And:

• Where Power Savings Really Count
• Making Electronics More Efficient (video)

Market Reports and Earnings

The semiconductor equipment industry is on a positive trajectory in 2024, with moderate revenue growth observed in Q2 after a subdued Q1, according to a new report from Yole Group. Wafer Fab Equipment revenue is projected to grow by 1.3% year-on-year, despite a 12% drop in Q1. Test equipment lead times are normalizing, improving order conditions. Key areas driving growth include memory and logic capital expenditures and high-bandwidth memory demand.

Worldwide silicon wafer shipments increased by 7% in Q2 2024, according to SEMI‘s latest report. This growth is attributed to robust demand from multiple semiconductor sectors, driven by advancements in AI, 5G, and automotive technologies.

The RF GaN market is projected to grow to US $2 billion by 2029, a 10% CAGR, according to Yole Group.

Counterpoint released their Q2 smartphone top 10 report.

Renesas completed their acquisition of EDA firm Altium, best known for its EDA platform and freeware CircuitMaker package.

It’s earnings season and here are recently released financials in the chip industry:

AMD  Advantest   Amkor   Ansys  Arteris   Arm   ASE   ASM   ASML
Cadence  IBM   Intel   Lam Research   Lattice   Nordson   NXP   Onsemi 
Qualcomm   Rambus  Samsung    SK Hynix   STMicro   Teradyne    TI  
Tower  TSMC    UMC  Western Digital

Industry stock price impacts are here.

Education and Training

Rochester Institute of Technology is leading a new pilot program to prepare community college students in areas such as cleanroom operations, new materials, simulation, and testing processes, with the intent of eventual transfer into RIT’s microelectronic engineering program.

Purdue University inked a deal with three research institutions — University of Piraeus, Technical University of Crete, and King’s College London —to develop joint research programs for semiconductors, AI and other critical technology fields.

The European Chips Skills Academy formed the Educational Leaders Board to help bridge the talent gap in Europe’s microelectronics sector.  The Board includes representatives from universities, vocational training providers, educators and research institutions who collaborate on strategic initiatives to strengthen university networks and build academic expertise through ECSA training programs.

Security

The Cybersecurity and Infrastructure Security Agency (CISA) is encouraging Apple users to review and apply this week’s recent security updates.

Microsoft Azure experienced a nearly 10 hour DDoS attack this week, leading to global service disruption for many customers.  “While the initial trigger event was a Distributed Denial-of-Service (DDoS) attack, which activated our DDoS protection mechanisms, initial investigations suggest that an error in the implementation of our defenses amplified the impact of the attack rather than mitigating it,” stated Microsoft in a release.

NIST published:

• “Recommendations For Increasing U.S. Participation and Leadership in Standards Development,” a report outlining cybersecurity recommendations and mitigation strategies.
• Final guidance documents and software to help improve the “safety, security and trustworthiness of AI systems.”
• Cloud Computing Forensic Reference Architecture guide.

Delta Air Lines plans to seek damages after losing $500 million in lost revenue due to security company CrowdStrike‘s software update debacle.  And shareholders are also angry.

Recent security research:

• Physically Secure Logic Locking With Nanomagnet Logic (UT Dallas)
• WBP: Training-time Backdoor Attacks through HW-based Weight Bit Poisoning (UCF)
• S-Tune: SOT-MTJ Manufacturing Parameters Tuning for Secure Next Generation of Computing ( U. of Arizona, UCF)
• Diffie Hellman Picture Show: Key Exchange Stories from Commercial VoWiFi Deployments (CISPA, SBA Research, U. of Vienna)

Product News

Lam Research introduced a new version of its cryogenic etch technology designed to enhance the manufacturing of 3D NAND for AI applications. This technology allows for the precise etching of high aspect ratio features, crucial for creating 1,000-layer 3D NAND.

Fig.1: 3D NAND etch. Source: Lam Research

Alphawave Semi launched its Universal Chiplet Interconnect Express Die-toDie IP. The subsystem offers 8 Tbps/mm bandwidth density and supports operation at 24 Gbps for D2D connectivity.

Infineon introduced a new MCU series for industrial and consumer motor controls, as well as power conversion system applications. The company also unveiled its new GoolGaN Drive product family of integrated single switches and half-bridges with integrated drivers.

Rambus released its DDR5 Client Clock Driver for next-gen, high-performance desktops and notebooks. The chips include Gen1 to Gen4 RCDs, power management ICs, Serial Presence Detect Hubs, and temperature sensors for leading-edge servers.

SK hynix introduced its new GDDR7 graphics DRAM. The product has an operating speed of 32Gbps, can process 1.5TB of data per second and has a 50% power efficiency improvement compared to the previous generation.

Intel launched its new Lunar Lake Ultra processors. The long awaited chips will be included in more than 80 laptop designs and has more than 40 NPU tera operations per second as well as over 60 GPU TOPS delivering more than 100 platform TOPS.

Brewer Science achieved recertification as a Certified B Corporation, reaffirming its commitment to sustainable and ethical business practices.

Panasonic adopted Siemens’ Teamcenter X cloud product lifecycle management solution, citing Teamcenter X’s Mendix low-code platform, improved operational efficiency and flexibility for its choice.

Keysight validated its 5G NR FR1 1024-QAM demodulation test cases for the first time. The 5G NR radio access technology supports eMBB and was validated on the 3GPP TS 38.521-4 test specification.

Research

In a 47-page deep-dive report, the Center for Security and Emerging Technology delved into all of the scientific breakthroughs from 1980 to present that brought EUV lithography to commercialization, including lessons learned for the next emerging technologies.

Researchers at the Paul Scherrer Institute developed a high-performance X-ray tomography technique using burst ptychography, achieving a resolution of 4nm. This method allows for non-destructive imaging of integrated circuits, providing detailed views of nanostructures in materials like silicon and metals.

MIT signed a four-year agreement with the Novo Nordisk Foundation Quantum Computing Programme at University of Copenhagen, focused on accelerating quantum computing hardware research.

MIT’s Research Laboratory of Electronics (RLE) developed a mechanically flexible wafer-scale integrated photonics fabrication platform. This enables the creation of flexible photonic circuits that maintain high performance while being bendable and stretchable. It offers significant potential for integrating photonic circuits into various flexible substrate applications in wearable technology, medical devices, and flexible electronics.

The Naval Research Lab identified a new class of semiconductor nanocrystals with bright ground-state excitons, emphasizing an important advancement in optoelectronics.

Researchers from National University of Singapore developed a novel method, known as tension-driven CHARM3D,  to fabricate 3D self-healing circuits, enabling the 3D printing of free-standing metallic structures without the need for support materials and external pressure.

Find more research in our Technical Papers library.

Events and Further Reading

Find upcoming chip industry events here, including:

Upcoming webinars are here, including topics such as quantum safe cryptography, analytics for high-volume manufacturing, and mastering EMC simulations for electronic design.

Find Semiconductor Engineering’s latest newsletters here:

Automotive, Security and Pervasive Computing
Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials

The post Chip Industry Week in Review appeared first on Semiconductor Engineering.

A new technical paper titled “An Evaluation of Continual Learning for Advanced Node Semiconductor Defect Inspection” was published by Imec and SCREEN SPE Germany.

Abstract

“Deep learning-based semiconductor defect inspection has gained traction in recent years, offering a powerful and versatile approach that provides high accuracy, adaptability, and efficiency in detecting and classifying nano-scale defects. However, semiconductor manufacturing processes are continually evolving, leading to the emergence of new types of defects over time. This presents a significant challenge for conventional supervised defect detectors, as they may suffer from catastrophic forgetting when trained on new defect datasets, potentially compromising performance on previously learned tasks. An alternative approach involves the constant storage of previously trained datasets alongside pre-trained model versions, which can be utilized for (re-)training from scratch or fine-tuning whenever encountering a new defect dataset. However, adhering to such a storage template is impractical in terms of size, particularly when considering High-Volume Manufacturing (HVM). Additionally, semiconductor defect datasets, especially those encompassing stochastic defects, are often limited and expensive to obtain, thus lacking sufficient representation of the entire universal set of defectivity. This work introduces a task-agnostic, meta-learning approach aimed at addressing this challenge, which enables the incremental addition of new defect classes and scales to create a more robust and generalized model for semiconductor defect inspection. We have benchmarked our approach using real resist-wafer SEM (Scanning Electron Microscopy) datasets for two process steps, ADI and AEI, demonstrating its superior performance compared to conventional supervised training methods.”

Find the technical paper here.  Published July 2024 (preprint).

Prasad, Amit, Bappaditya Dey, Victor Blanco, and Sandip Halder. “An Evaluation of Continual Learning for Advanced Node Semiconductor Defect Inspection.” arXiv preprint arXiv:2407.12724 (2024).

The post Classification and Localization of Semiconductor Defect Classes in Aggressive Pitches (imec, Screen) appeared first on Semiconductor Engineering.

As Intel, Samsung, TSMC, and Japan’s upcoming advanced foundry Rapidus each make their separate preparations to cram more and more transistors into every square millimeter of silicon, one thing they all have in common is that the extreme ultraviolet (EUV) lithography technology underpinning their efforts is extremely complex, extremely expensive, and extremely costly to operate. A prime reason is that the source of this system’s 13.5-nanometer light is the precise and costly process of blasting flying droplets of molten tin with the most powerful commercial lasers on the planet.

But an unconventional alternative is in the works. A group of researchers at the High Energy Accelerator Research Organization, known as KEK, in Tsukuba, Japan, is betting EUV lithography might be cheaper, quicker, and more efficient if it harnesses the power of a particle accelerator.

Even before the first EUV machines had been installed in fabs, researchers saw possibilities for EUV lithography using a powerful light source called a free-electron laser (FEL), which is generated by a particle accelerator. However, not just any particle accelerator will do, say the scientists at KEK. They claim the best candidate for EUV lithography incorporates the particle-accelerator version of regenerative braking. Known as an energy recovery linear accelerator, it could enable a free electron laser to economically generate tens of kilowatts of EUV power. This is more than enough to drive not one but many next-generation lithography machines simultaneously, pushing down the cost of advanced chipmaking.

“The FEL beam’s extreme power, its narrow spectral width, and other features make it suitable as an application for future lithography,” Norio Nakamura, researcher in advanced light sources at KEK, told me on a visit to the facility.

Linacs Vs. Laser-Produced Plasma

Today’s EUV systems are made by a single manufacturer, ASML, headquartered in Veldhoven, Netherlands. When ASML introduced the first generation of these US $100-million-plus precision machines in 2016, the industry was desperate for them. Chipmakers had been getting by with workaround after workaround for the then most advanced system, lithography using 193-nm light. Moving to a much shorter, 13.5-nm wavelength was a revolution that would collapse the number of steps needed in chipmaking and allow Moore’s Law to continue well into the next decade.

The chief cause of the continual delays was a light source that was too dim. The technology that ultimately delivered a bright enough source of EUV light is called laser-produced plasma, or EUV-LPP. It employs a carbon dioxide laser to blast molten droplets of tin into plasma thousands of times per second. The plasma emits a spectrum of photonic energy, and specialized optics then capture the necessary 13.5-nm wavelength from the spectrum and guide it through a sequence of mirrors. Subsequently, the EUV light is reflected off a patterned mask and then projected onto a silicon wafer.

The experimental compact energy recovery linac at KEK uses most of the energy from electrons on a return journey to speed up a new set of electrons.KEK

It all adds up to a highly complex process. And although it starts off with kilowatt-consuming lasers, the amount of EUV light that is reflected onto the wafer is just several watts. The dimmer the light, the longer it takes to reliably expose a pattern on the silicon. Without enough photons carrying the pattern, EUV would be uneconomically slow. And pushing too hard for speed can lead to costly errors.

When the machines were first introduced, the power level was enough to process about 100 wafers per hour. Since then, ASML has managed to steadily hike the output to about 200 wafers per hour for the present series of machines.

ASML’s current light sources are rated at 500 watts. But for the even finer patterning needed in the future, Nakamura says it could take 1 kilowatt or more. ASML says it has a road map to develop a 1,000-W light source. But it could be difficult to achieve, says Nakamura, who formerly led the beam dynamics and magnet group at KEK and came out of retirement to work on the EUV project.

Difficult but not necessarily impossible. Doubling the source power is “very challenging,” agrees Ahmed Hassanein who leads the Center for Materials Under Extreme Environment, at Purdue University, in Indiana. But he points out that ASML has achieved similarly difficult targets in the past using an integrated approach of improving and optimizing the light source and other components, and he isn’t ruling out a repeat.

In a free electron laser, accelerated electrons are subject to alternating magnetic fields, causing them to undulate and emit electromagnetic radiation. The radiation bunches up the electrons, leading to their amplifying only a specific wavelength, creating a laser beam.Chris Philpot

But brightness isn’t the only issue ASML faces with laser-produced plasma sources. “There are a number of challenging issues in upgrading to higher EUV power,” says Hassanein. He rattles off several, including “contamination, wavelength purity, and the performance of the mirror-collection system.”

High operating costs are another problem. These systems consume some 600 liters of hydrogen gas per minute, most of which goes into keeping tin and other contaminants from getting onto the optics and wafers. (Recycling, however, could reduce this figure.)

But ultimately, operating costs come down to electricity consumption. Stephen Benson, recently retired senior research scientist at the Thomas Jefferson National Accelerator Facility, in Virginia., estimates that the wall-plug efficiency of the whole EUV-LPP system might be less than 0.1 percent. Free electron lasers, like the one KEK is developing, could be as much as 10 to 100 times as efficient, he says.

The Energy Recovery Linear Accelerator

The system KEK is developing generates light by boosting electrons to relativistic speeds and then deviating their motion in a particular way.

The process starts, Nakamura explains, when an electron gun injects a beam of electrons into a meters-long cryogenically cooled tube. Inside this tube, superconductors deliver radio-frequency (RF) signals that drive the electrons along faster and faster. The electrons then make a 180-degree turn and enter a structure called an undulator, a series of oppositely oriented magnets. (The KEK system currently has two.) The undulators force the speeding electrons to follow a sinusoidal path, and this motion causes the electrons to emit light.

In linear accelerator, injected electrons gain energy from an RF field. Ordinarily, the electrons would then enter a free electron laser and are immediately disposed of in a beam dump. But in an energy recovery linear accelerator (ERL), the electrons circle back into the RF field and lend their energy to newly injected electrons before exiting to a beam dump.

What happens next is a phenomenon called self-amplified spontaneous emissions, or SASE. The light interacts with the electrons, slowing some and speeding up others, so they gather into “microbunches,” peaks in density that occur periodically along the undulator’s path. The now-structured electron beam amplifies only the light that’s in phase with the period of these microbunches, generating a coherent beam of laser light.

It’s at this point that KEK’s compact energy recovery linac (cERL), diverges from lasers driven by conventional linear accelerators. Ordinarily, the spent beam of electrons is disposed of by diverting the particles into what is called a beam dump. But in the cERL, the electrons first loop back into the RF accelerator. This beam is now in the opposite phase to newly injected electrons that are just starting their journey. The result is that the spent electrons transfer much of their energy to the new beam, boosting its energy. Once the original electrons have had some of their energy drained away like this, they are diverted into a beam dump.

“The acceleration energy in the linac is recovered, and the dumped beam power is drastically reduced compared to [that of] an ordinary linac,” Nakamura explains to me while scientists in another room operate the laser. Reusing the electrons’ energy means that for the same amount of electricity the system sends more current through the accelerator and can fire the laser more frequently, he says.

Other experts agree. The energy-recovery linear accelerator’s improved efficiency can lower costs, “which is a major concern of using EUV laser-produced plasma,” says Hassanein.

The Energy Recovery Linac for EUV

The KEK compact energy-recovery linear accelerator was initially constructed between 2011 and 2013 with the aim of demonstrating its potential as a synchrotron radiation source for researchers working for the institution’s physics and materials-science divisions. But researchers were dissatisfied with the planned system, which had a lower performance target than could be achieved by some storage ring-based synchrotrons—huge circular accelerators that keep a beam of electrons moving with a constant kinetic energy. So, the KEK researchers went in search of a more appropriate application. After talking with Japanese tech companies, including Toshiba, which had a flash memory chip division at the time, the researchers conducted an initial study that confirmed that a kilowatt-class light source was possible with a compact energy-recovery linear accelerator. And so, the EUV free-electron-laser project was born. In 2019 and 2020, the researchers modified the existing experimental accelerator to start the journey to EUV light.

The system is housed in an all-concrete room to protect researchers from the intense electromagnetic radiation produced during operation. The room is some 60 meters long and 20 meters wide with much of the space taken up by a bewildering tangle of complex equipment, pipes, and cables that snakes along both sides of its length in the form of an elongated racetrack.

The accelerator is not yet able to generate EUV wavelengths. With an electron beam energy of 17 megaelectronvolts, the researchers have been able to generate SASE emissions in bursts of 20-micrometer infrared light. Early test results were published in the Japanese Journal of Applied Physics in April 2023. The next step, which is underway, is to generate much greater laser power in continuous-wave mode.

To be sure, 20 micrometers is a far cry from 13.5 nanometers. And there are already types of particle accelerators that produce synchrotron radiation of even shorter wavelengths than EUV. But lasers based on energy-recovery linear accelerators could generate significantly more EUV power due to their inherent efficiency, the KEK researchers claim. In synchrotron radiation sources, light intensity increases proportionally to the number of injected electrons. By comparison, in free-electron laser systems, light intensity increases roughly with the square of the number of injected electrons, resulting in much more brightness and power.

For an energy-recovery linear accelerator to reach the EUV range will require equipment upgrades beyond what KEK currently has room for. So, the researchers are now making the case for constructing a new prototype system that can produce the needed 800 MeV.

An electron gun injects charge into the compact energy recovery linear accelerator at KEK.KEK

In 2021, before severe inflation affected economies around the globe, the KEK team estimated the construction cost (excluding land) for a new system at 40 billion yen ($260 million) for a system that delivers 10 kW of EUV and supplies multiple lithography machines. Annual running costs were judged to be about 4 billion yen. So even taking recent inflation into account, “the estimated costs per exposure tool in our setup are still rather low compared to the estimated costs” for today’s laser-produced plasma source, says Nakamura.

There are plenty of technical challenges to work out before such a system can achieve the high levels of performance and stability of operations demanded by semiconductor manufacturers, admits Nakamura. The team will have to develop new editions of key components such as the superconducting cavity, the electron gun, and the undulator. Engineers will also have to develop good procedural techniques to ensure, for instance, that the electron beam does not degrade or falter during operations.

And to ensure their approach is cost effective enough to grab the attention of chipmakers, the researchers will need to create a system that can reliably transport more than 1 kW of EUV power simultaneously to multiple lithography machines. The researchers already have a conceptual design for an arrangement of special mirrors that would convey the EUV light to multiple exposure tools without significant loss of power or damage to the mirrors.

Other EUV Possibilities

It’s too early in the development of EUV free-electron lasers for rapidly expanding chipmakers to pay it much attention. But the KEK team is not alone in chasing the technology. A venture-backed startup xLight, in Palo Alto, Calif. is also among those chasing it. The company, which is packed with particle-accelerator veterans from the Stanford Linear Accelerator and elsewhere, recently inked an R&D deal with Fermi National Accelerator Laboratory, in Illinois, to develop superconducting cavities and cryomodule technology. Attempts to contact xLight went unanswered, but in January, the company took part in the 8th Workshop EUV-FEL in Tokyo, and former CEO Erik Hosler gave a presentation on the technology.

Significantly, ASML considered turning to particle accelerators a decade ago and again more recently when it compared the progress of free-electron laser technology to the laser-produced plasma road map. But company executives decided LLP presented fewer risks.

And, indeed, it is a risky road. Independent views on KEK’s project emphasize that reliability and funding will be the biggest challenges the researchers face going forward. “The R&D road map will involve numerous demanding stages in order to develop a reliable, mature system,” says Hassanein. “This will require serious investment and take considerable time.”

“The machine design must be extremely robust, with redundancy built in,” adds retired research scientist Benson. The design must also ensure that components are not damaged from radiation or laser light.” And this must be accomplished “without compromising performance, which must be good enough to ensure decent wall-plug efficiency.”

More importantly, Benson warns that without a forthcoming commitment to invest in the technology, “development of EUV-FELs might not come in time to help the semiconductor industry.”

The eBeam initiative celebrated its 15^th anniversary at the recent SPIE Advanced Lithography + Patterning Conference. 130 members of the mask and lithography community attended the annual lunch to mark the milestone. The eBeam Initiative welcomed its 53^rd member, FUJIFILM Corporation, having grown from 20 members and advisors at its launch. FUJIFILM is the first company from the chemical supply chain and recognizes the defacto role resist plays to the eBeam community. Two of our founding members, Matthias Slodowski from Vistec Electron Beam and Aki Fujimura from D2S and co-founder of the eBeam Initiative, made presentations that illustrated the evolution of eBeam and lithography technologies over the past 15 years.  In fact, at the end of Aki’s recap of eBeam innovation,  there was a standing ovation recognizing how much the mask and lithography segments have achieved in the past 15 years.

Fig. 1: Aki Fujimura, CEO of D2S and co-founder of the eBeam Initiative, highlights major eBeam technology innovations over the past 15 years of the eBeam Initiative.

Aki recognized over 80 individuals who have contributed educational content over the past 15 years, whether it be a presentation, video, article or panel discussion. His timeline presentation highlighted key lithography and photomask developments over this period. In the first 5-6 years, the focus was on alternative lithography solutions while the world waited to see if EUV became real. In particular, eBeam direct write was a hot topic. It’s nice to see that 15 years later, that approach has found new applications in advanced packaging, chip security, and high-performance computing to name a few, as Matthias highlighted in a video of his talk (figure 2).

Fig. 2: Matthias Slodowski of Vistec Electron Beam, a founding member of the eBeam Initiative, recaps how cell projection has evolved and describes optical and photonics mastering applications. 

In 2012, the annual eBeam Initiative survey of industry luminaries was launched, asking for their opinions about key trends and requirements in the future. While many of them couldn’t answer questions publicly about what they think, they could answer anonymously to project future trends. In 2015, the survey reflected the turning point for EUV, several years before it became a reality.

Another important development happening at the same time as EUV was the pivot to develop multi-beam mask writers, with the attribute of constant write time no matter what shape you write. This was a contributing factor to the next major trend emerging from 2019… Curvilinear masks. In addition to multibeam mask writing for providing the speed to write curvilinear masks, you need fast full-chip curvilinear ILT software (think ILT in a day) to derive the mask patterns from the shapes you actually get on wafers. As of the 2023 Luminaries survey, 87% thought leading photomask manufacturers could meet the demand for curvilinear masks.

On the day of the lunch, the eBeam Initiative published the fourth annual Deep Learning survey of members products and applications using deep learning (DL) in the photomask to wafer manufacturing flow. Two new members reported this year, DNP and Synopsys, bringing the total to 15 members reporting. Tom Cecil of Synopsys describes in a new eBeam Initiative video how three key areas of AI-driven EDA – optimization, analytics, and generative AI – can be useful across the design-to-manufacturing space, including within the mask synthesis domain (figure 3). Looking at the DL report, it’s clear that speed is the key benefit of applying DL and many applications involve SEM images. But DL is also for accuracy as some members like ASML have pointed out at past lunch events.

Fig. 3: Tom Cecil from Synopsys on AI-Driven EDA.

If the past 15 years is any predictor, the eBeam community will continue to evolve solutions in ways we haven’t thought of yet. In the mid-term, the capability of manufacturing to deliver curvilinear masks is enabling the design community to pursue curvilinear design. Thanks to the diversity of the solutions on the design side, like chiplets, there will be new opportunities for the manufacturing chain. Some of the luminaries in the eBeam community spoke about this and other projections for the next 15 years in a new video (figure 4).

Fig. 4: Luminaries share their perspective on the eBeam Initiative past and future.

15 years ago, the eBeam Initiative focused on the message that eBeam writes all chips. That’s still true today and will be true in 15 years.

The post eBeam Initiative Marks Major Milestones Over 15 Years Of Photomasks And Lithography appeared first on Semiconductor Engineering.

Abstract:

“Full-chip curvilinear inverse lithography technology (ILT) requires mask writers to write full reticle curvilinear mask patterns in a reasonable write time. We jointly study and present the benefits of a full-chip, curvilinear, stitchless ILT with mask-wafer co-optimization (MWCO) for variable-shaped beam (VSB) mask writers and validate its benefits on mask and wafer at Micron Technology. The full-chip ILT technology employed, first demonstrated in a paper presented at the 2019 SPIE Photomask Technology Conference, produces curvilinear ILT mask patterns without stitching errors, and with process windows enlarged by over 100% compared to the OPC process of record, while the mask was written by multibeam mask writer. At the 2020 SPIE Advanced Lithography Conference, a method was introduced in which MWCO is performed during ILT optimization. This approach enables curvilinear ILT for 193i masks to be written on VSB mask writers within a practical, 12-h time frame, while also producing the largest process windows. We first review MWCO technology, then curvilinear ILT mask patterns written by VSB mask writer, and then show the corresponding 193i process wafer prints. Evaluations of mask write times and mask quality in terms of critical dimension uniformity and process windows are also presented.”

Find the technical paper here. Published February 2024.

Pang, Linyong, Sha Lu, Ezequiel Vidal Russell, Yang Lu, Michael Lee, Jennefir Digaum, Ming-Chuan Yang et al. “Make the impossible possible: use variable-shaped beam mask writers and curvilinear full-chip inverse lithography technology for 193i contacts/vias with mask-wafer co-optimization.” Journal of Micro/Nanopatterning, Materials, and Metrology 23, no. 1 (2024): 011207-011207.

Author Affiliations: D2S Inc. and Micron Technology Inc.

The post Make The Impossible Possible: Use Variable-Shaped Beam Mask Writers And Curvilinear Full-Chip Inverse Lithography Technology For 193i Contacts/Vias With Mask-Wafer Co-Optimization appeared first on Semiconductor Engineering.

This white paper identifies and discusses the computational needs required to support the development, optimization, and implementation of high NA extreme ultraviolet (EUV) lithography. It explores the challenges associated with the increased complexity of high NA systems, proposes potential solutions, and highlights the importance of computational lithography in driving the success of advanced EUV lithography technologies.

Click here to read more.

The post Computational Lithography Solutions To Enable High NA EUV appeared first on Semiconductor Engineering.