BAE Systems and GlobalFoundries are teaming up to strengthen the supply of chips for national security programs, aligning technology roadmaps and collaborating on innovation and manufacturing. Focus areas include advanced packaging, GaN-on-silicon chips, silicon photonics, and advanced technology process development.

Onsemi plans to build a $2 billion silicon carbide production plant in the Czech Republic. The site would produce smart power semiconductors for electric vehicles, renewable energy technology, and data centers.

The global chip manufacturing industry is projected to boost capacity by 6% in 2024 and 7% in 2025, reaching 33.7 million 8-inch (200mm) wafers per month, according to SEMI‘s latest World Fab Forecast report. Leading-edge capacity for 5nm nodes and below is expected to grow by 13% in 2024, driven by AI demand for data center applications. Additionally, Intel, Samsung, and TSMC will begin producing 2nm chips using gate-all-around (GAA) FETs next year, boosting leading-edge capacity by 17% in 2025.

At the IEEE Symposium on VLSI Technology & Circuits, imec introduced:

• Functional CMOS-based CFETs with stacked bottom and top source/drain contacts.
• CMOS-based 56Gb/s zero-IF D-band beamforming transmitters to support next-gen short-range, high-speed wireless services at frequencies above 100GHz.
• ADCs for base stations and handsets, a key step toward scalable, high-performance beyond-5G solutions, such as cloud-based AI and extended reality apps.

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Global

Wolfspeed postponed plans to construct a $3 billion chip plant in Germany, underscoring the EU‘s challenges in boosting semiconductor production, reports Reuters. The North Carolina-based company cited reduced capital spending due to a weakened EV market, saying it now aims to start construction in mid-2025, two years later than 0riginally planned.

Micron is building a pilot production line for high-bandwidth memory (HBM) in the U.S., and considering HBM production in Malaysia to meet growing AI demand, according to a Nikkei report. The company is expanding HBM R&D facilities in Boise, Idaho, and eyeing production capacity in Malaysia, while also enhancing its largest HBM facility in Taichung, Taiwan.

Kioxia restored its Yokkaichi and Kitakami plants in Japan to full capacity, ending production cuts as the memory market recovers, according to Nikkei. The company, which is focusing on NAND flash production, has secured new bank credit support, including refinancing a ¥540 billion loan and establishing a ¥210 billion credit line. Kioxia had reduced output by more than 30% in October 2022 due to weak smartphone demand.

Europe’s NATO Innovation Fund announced its first direct investments, which includes semiconductor materials. Twenty-three NATO allies co-invested in this over $1B fund devoted to address critical defense and security challenges.

The second meeting of the U.S.–India Initiative on Critical and Emerging Technology (iCET) was held in New Delhi, with various funding and initiatives announced to support semiconductor technology, next-gen telecommunications, connected and autonomous vehicles, ML, and more.

Amazon announced investments of €10 billion in Germany to drive innovation and support the expansion of its logistics network and cloud infrastructure.

Quantum Machines opened the Israeli Quantum Computing Center (IQCC) research facility, backed by the Israel Innovation Authority and located at Tel Aviv University. Also, Israel-based Classiq is collaborating with NVIDIA and BMW, using quantum computing to find the optimal automotive architecture of electrical and mechanical systems.

Global data center vacancy rates are at historic lows, and power availability is becoming less available, according to a Siemens report featured on Broadband Breakfast. The company called for an influx of financing to find new ways to optimize data center technology and sustainability.

In-Depth

Semiconductor Engineering published its Manufacturing, Packaging & Materials newsletter this week, featuring these top stories:

• Single Vs. Multi-Patterning Advancements For EUV
• Precise Control Of Copper Plating And CMP
• Ruthenium Interconnects On Tap
• Opportunities Grow For GPU Acceleration

More reporting this week:

• IC Industry’s Growing Role In Sustainability
• What’s Missing In Test

Market Reports

Renesas completed its acquisition of Transphorm and will immediately start offering GaN-based power products and reference designs to meet the demand for wide-bandgap (WBG) chips.

Revenues for the top five wafer fab equipment (WFE) companies fell 9% YoY in Q1 2024, according to Counterpoint. This was offset partially by increased demand for NAND and DRAM, which increased 33% YoY, and strong growth in sales to China, which were up 116% YoY.

The SiC power devices industry saw robust growth in 2023, primarily driven by the BEV market, according to TrendForce. The top five suppliers, led by ST with a 32.6% market share and onsemi in second place, accounted for 91.9% of total revenue. However, the anticipated slowdown in BEV sales and weakening industrial demand are expected to significantly decelerate revenue growth in 2024. 

About 30% of vehicles produced globally will have E/E architectures with zonal controllers by 2032, according to McKinsey & Co. The market for automotive micro-components and logic semiconductors is predicted to reach $60 billion in 2032, and the overall automotive semiconductor market is expected to grow from $60 billion to $140 billion in the same period, at a 10% CAGR.

The automotive processor market generated US$20 billion in revenue in 2023, according to Yole. US$7.8 billion was from APUs and FPGAs and $12.2 billion was from MCUs. The ADAS and infotainment processors market was worth US$7.8 billion in 2023 and is predicted to grow to $16.4 billion by 2029 at a 13% CAGR. The market for ADAS sensing is expected to grow at a 7% CAGR.

Security

The CHERI Alliance was established to drive adoption of memory safety and scalable software compartmentalization via the security technology CHERI, or Capability Hardware Enhanced RISC Instructions. Founding members include Capabilities Limited, Codasip, the FreeBSD Foundation, lowRISC, SCI Semiconductor, and the University of Cambridge.

In security research:

• Japan and China researchers explored a NAND-XOR ring oscillator structure to design an entropy source architecture for a true random number generator (TRNG).
• University of Toronto and Carleton University researchers presented a survey examining how hardware is applied to achieve security and how reported attacks have exploited certain defects in hardware.
• University of North Texas and Texas Woman’s University researchers explored the potential of hardware security primitive Physical Unclonable Functions (PUF) for mitigation of visual deepfakes.
• Villanova University researchers proposed the Boolean DERIVativE attack, which generalizes Boolean domain leakage.

Post-quantum cryptography firm PQShield raised $37 million in Series B funding.

Former OpenAI executive, Ilya Sutskever, who quit over safety concerns, launched Safe Superintelligence Inc. (SSI).

EU industry groups warned the European Commission that its proposed cybersecurity certification scheme (EUCS) for cloud services should not discriminate against Amazon, Google, and Microsoft, reported Reuters.

Cyber Europe tested EU cyber preparedness in the energy sector by simulating a series of large-scale cyber incidents in an exercise organized by the European Union Agency for Cybersecurity (ENISA).

The Cybersecurity and Infrastructure Security Agency (CISA) issued a number of alerts/advisories.

Education and Training

New York non-profit NY CREATES and South Korea’s National Nano Fab Center partnered to develop a hub for joint research, aligned technology services, testbed support, and an engineer exchange program to bolster chips-centered R&D, workforce development, and each nation’s high-tech ecosystem.

New York and the Netherlands agreed on a partnership to promote sustainability within the semiconductor industry, enhance workforce development, and boost semiconductor R&D.

Rapidus is set to send 200 engineers to AI chip developer Tenstorrent in the U.S. for training over the next five years, reports Nikkei. This initiative, led by Japan’s Leading-edge Semiconductor Technology Center (LSTC), aims to bolster Japan’s AI chip industry.

Product News

UMC announced its 22nm embedded high voltage (eHV) technology platform for premium smartphone and mobile device displays. The 22eHV platform reduces core device power consumption by up to 30% compared to previous 28nm processes. Die area is reduced by 10% with the industry’s smallest SRAM bit cells.​

Alphawave Semi announced a new 9.2 Gbps HBM3E sub-system silicon platform capable of 1.2 terabytes per second. Based on the HBM3E IP, the sub-system is aimed at addressing the demand for ultra-high-speed connectivity in high-performance compute applications.

Movellus introduced the Aeonic Power product family for on-die voltage regulation, targeting the challenging area of power delivery.

Cadence partnered with Semiwise and sureCore to develop new cryogenic CMOS circuits with possible quantum computing applications. The circuits are based on modified transistors found in the Cadence Spectre Simulation Platform and are capable of processing analog, mixed-signal, and digital circuit simulation and verification at cryogenic temperatures.

Renesas launched R-Car Open Access (RoX), an integrated development platform for software-defined vehicles (SDVs), designed for Renesas R-Car SoCs and MCUs with tools for deployment of AI applications, reducing complexity and saving time and money for car OEMs and Tier 1s.

Infineon released industry-first radiation-hardened 1 and 2 Mb parallel interface ferroelectric-RAM (F-RAM) nonvolatile memory devices, with up to 120 years of data retention at 85-degree Celsius, along with random access and full memory write at bus speeds. Plus, a CoolGaN Transistor 700 V G4 product family for efficient power conversion up to 700 V, ideal for consumer chargers and notebook adapters, data center power supplies, renewable energy inverters, and more.

Ansys adopted NVIDIA’s Omniverse application programming interfaces for its multi-die chip designers. Those APIs will be used for 5G/6G, IoT, AI/ML, cloud computing, and autonomous vehicle applications. The company also announced ConceptEV, an SaaS solution for automotive concept design for EVs.

Fig. 1: Field visualization of 3D-IC with Omniverse. Source: Ansys

QP Technologies announced a new dicing saw for its manufacturing line that can process a full cassette of 300mm wafers 7% faster than existing tools, improving throughput and productivity.

NXP introduced its SAF9xxx of audio DSPs to support the demand for AI-based audio in software-defined vehicles (SDVs) by using Cadence’s Tensilica HiFi 5 DSPs combined with dedicated neural-network engines and hardware-based accelerators.

Avionyx, a provider of software lifecycle engineering in the aerospace and safety-critical systems sector, partnered with Siemens and will leverage its Polarion application lifecycle management (ALM) tool. Also, Dovetail Electric Aviation adopted Siemens Xcelerator to support sustainable aviation.

Research

Researchers from imec and KU Leuven released a +70 page paper “Selecting Alternative Metals for Advanced Interconnects,” addressing interconnect resistance and reliability.

A comprehensive review article — “Future of plasma etching for microelectronics: Challenges and opportunities” — was created by a team of experts from the University of Maryland, Lam Research, IBM, Intel, and many others.

Researchers from the Institut Polytechnique de Paris’s Laboratory of Condensed Matter for Physics developed an approach to investigate defects in semiconductors. The team “determined the spin-dependent electronic structure linked to defects in the arrangement of semiconductor atoms,” the first time this structure has been measured, according to a release.

Lawrence Berkeley National Laboratory-led researchers developed a small enclosed chamber that can hold all the components of an electrochemical reaction, which can be paired with transmission electron microscopy (TEM) to generate precise views of a reaction at atomic scale, and can be frozen to stop the reaction at specific time points. They used the technique to study a copper catalyst.

The Federal Drug Administration (FDA) approved a clinical trial to test a device with 1,024 nanoscale sensors that records brain activity during surgery, developed by engineers at the University of California San Diego (UC San Diego).

Events and Further Reading

Find upcoming chip industry events here, including:

Upcoming webinars are here.

Semiconductor Engineering’s latest newsletters:

Automotive, Security and Pervasive Computing
Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials

The post Chip Industry Week In Review appeared first on Semiconductor Engineering.

Rapidus and IBM are jointly developing mass production capabilities for chiplet-based advanced packages. The collaboration builds on an existing agreement to develop 2nm process technology.

Vanguard and NXP will jointly establish VisionPower Semiconductor Manufacturing Company (VSMC) in Singapore to build a $7.8 billion, 12-inch wafer plant. This is part of a global supply chain shift “Out of China, Out of Taiwan,” according to TrendForce.

Alphawave joined forces with Arm to develop an advanced chiplet based on Arm’s Neoverse Compute Subystems for AI/ML. The chiplet contains the Neoverse N3 CPU core cluster and Arm Coherent Mesh Network, and will be targeted at HPC in data centers, AI/ML applications, and 5G/6G infrastructure.

ElevATE Semiconductor and GlobalFoundries will partner for high-voltage chips to be produced at GF’s facility in Essex Junction, Vermont, which GF bought from IBM. The chips are essential for semiconductor testing equipment, aerospace, and defense systems.

NVIDIA, OpenAI, and Microsoft are under investigation by the U.S. Federal Trade Commission and Justice Department for violation of antitrust laws in the generative AI industry, according to the New York Times.

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Apollo Global Management will invest $11 billion in Intel’s Fab 34 in Ireland, thereby acquiring a 49% stake in Intel’s Irish manufacturing operations.

imec and ASML opened their jointly run High-NA EUV Lithography Lab in Veldhoven, the Netherlands. The lab will be used to prepare  the next-generation litho for high-volume manufacturing, expected to begin in 2025 or 2026.

Expedera opened a new semiconductor IP design center in India. The location, the sixth of its kind for the company, is aimed at helping to make up for a shortfall in trained technicians, researchers, and engineers in the semiconductor sector.

Foxconn will build an advanced computing center in Taiwan with NVIDIA’s Blackwell platform at its core. The site will feature GB200 servers, which consist of 64 racks and 4,608 GPUs, and will be completed by 2026.

Intel and its 14 partner companies in Japan will use Sharp‘s LCD plants to research semiconductor production technology, a cost reduction move that should also produce income for Sharp, according to Nikkei Asia.

Japan is considering legislation to support the commercial production of advanced semiconductors, per Reuters.

Saudi Arabia aims to establish at least 50 semiconductor design companies as part of a new National Semiconductor Hub, funded with over $266 million.

Air Liquide is opening a new industrial gas production facility in Idaho, which will produce ultra-pure nitrogen and other gases for Micron’s new fab.

Microsoft will invest 33.7 billion Swedish crowns ($3.2 billion) to expand its cloud and AI infrastructure in Sweden over a two-year period, reports Bloomberg. The company also will invest $1 billion to establish a new data center in northwest Indiana.

AI data centers could consume as much as 9.1% of the electricity generated in the U.S. by 2030, according to a white paper published by the Electric Power Research Institute. That would more than double the electricity currently consumed by data centers, though EPRI notes this is a worst case scenario and advances in efficiency could be a mitigating factor.

Markets and Money

The Semiconductor Industry Association (SIA) announced global semiconductor sales increased 15.8% year-over-year in April, and the group projected a market growth of 16% in 2024. Conversely, global semiconductor equipment billings contracted 2% year-over-year to US$26.4 billion in Q1 2024, while quarter-over-quarter billings dropped 6% during the same period, according to SEMI‘s Worldwide Semiconductor Equipment Market Statistics (WWSEMS) Report.

Cadence completed its acquisition of BETA CAE Systems International, a provider of multi-domain, engineering simulation solutions.

Cisco‘s investment arm launched a $1 billion fund to aid AI startups as part of its AI innovation strategy. Nearly $200 million has already been earmarked.

The power and RF GaN markets will grow beyond US$2.45 billion and US$1.9 billion in 2029, respectively, according to Yole, which is offering a webinar on the topic.

The micro LED chip market is predicted to reach $580 million by 2028, driven by head-mounted devices and automotive applications, according to TrendForce. The cost of Micro LED chips may eventually come down due to size miniaturization.

In-Depth

Semiconductor Engineering published its Automotive, Security, and Pervasive Computing newsletter this week, featuring these top stories:

• The Uncertainty Of Certifying AI For Automotive
• Why It’s So Hard To Secure AI Chips
• Toward A Software-Defined Hardware World

More reporting this week:

• Chip Design Digs Deeper Into AI
• Why IC Design Safety Nets Have Limits
• Opportunities Grow For GPU Acceleration

Security

Scott Best, Rambus senior director of Silicon Security Products, delivered a keynote at the Hardwear.io conference this week (below), detailing a $60 billion reverse engineering threat for hardware in just three markets — $30 billion for printer consumables, $20 billion for rechargeable batteries with some type of authentication, and $10 billion for medical devices such as sonogram probes.

Photo source: Ed Sperling/Semiconductor Engineering

wolfSSL debuted wolfHSM for automotive hardware security modules, with its cryptographic library ported to run in automotive HSMs like Infineon’s Aurix Tricore TC3XX.

Cisco integrated AMD Pensando data processing units (DPUs) with its Hypershield security architecture for defending AI-scale data centers.

OMNIVISION released an intelligent CMOS image sensor for human presence detection, infrared facial authentication, and always-on technology with a single sensing camera. And two new image sensors for industrial and consumer security surveillance cameras.

Digital Catapult announced a new cohort of companies will join Digital Security by Design’s Technology Access Program, gaining access to an Arm Morello prototype evaluation hardware kit based on Capability Hardware Enhanced RISC Instructions (CHERI), to find applications across critical UK sectors.

University of Southampton researchers used formal verification to evaluate the hardware reliability of a RISC-V ibex core in the presence of soft errors.

Several institutions published their students’ master’s and PhD work:

• Virginia Tech published a dissertation proposing sPACtre, a defense mechanism that aims to prevent Spectre control-flow attacks on existing hardware.
• Wright State University published a thesis proposing an approach that uses various machine learning models to bring an improvement in hardware Trojan identification with power signal side channel analysis
• Wright State University published a thesis examining the effect of aging on the reliability of SRAM PUFs used for secure and trusted microelectronics IC applications.
• Nanyang Technological University published a Final Year Project proposing a novel SAT-based circuit preprocessing attack based on the concept of logic cones to enhance the efficacy of SAT attacks on complex circuits like multipliers.

The Cybersecurity and Infrastructure Security Agency (CISA) issued a number of alerts/advisories.

Education and Training

Renesas and the Indian Institute of Technology Hyderabad (IIT Hyderabad) signed a three-year MoU to collaborate on VLSI and embedded semiconductor systems, with a focus on R&D and academic interactions to advance the “Make in India” strategy.

Charlie Parker, senior machine learning engineer at Tignis, presented a talk on “Why Every Fab Should Be Using AI.”

Penn State and the National Sun Yat-Sen University (NSYSU) in Taiwan partnered to develop educational and research programs focused on semiconductors and photonics.

Rapidus and Hokkaido University partnered on education and research to enhance Japan’s scientific and technological capabilities and develop human resources for the semiconductor industry.

The University of Minnesota named Steve Koester its first “Chief Semiconductor Officer,” and launched a website devoted to semiconductor and microelectronics research and education.

The state of Michigan invested $10 million toward semiconductor workforce development.

Product News

Siemens reported breakthroughs in high-level C++ verification that will be used in conjunction with its Catapult software. Designers will be able to use formal property checking via the Catapult Formal Assert software and reachability coverage analysis through Catapult Formal CoverCheck.

Infineon released several products:

• 600 V CoolMOS 8 high voltage superjunction (SJ) MOSFET product family.
• CoolGaN bidirectional switch (BDS) and CoolGaN Smart Sense device.
• New CoolSiC MOSFET discretes 650 V, with two product families housed in the Thin-TOLL 8×8 and TOLT packages to increase system power density.

Augmental, an MIT Media Lab spinoff, released a tongue-based computer controller, dubbed the MouthPad.

NVIDIA revealed a new line of products that will form the basis of next-gen AI data centers. Along with partners ASRock Rack, ASUS, GIGABYTE, Ingrasys, and others, the NVIDIA GPUs and networking tech will offer cloud, on-premises, embedded, and edge AI systems. NVIDIA founder and CEO Jensen Huang showed off the company’s upcoming Rubin platform, which will succeed its current Blackwell platform. The new system will feature new GPUs, an Arm-based CPU and advanced networking with NVLink 6, CX9 SuperNIC and X1600 converged InfiniBand/Ethernet switch.

Intel showed off its Xeon 6 processors at Computex 2024. The company also unveiled architectural details for its Lunar Lake client computing processor, which will use 40% less SoC power, as well as a new NPU, and X2 graphic processing unit cores for gaming.

Research

imec released a roadmap for superconducting digital technology to revolutionize AI/ML.

CEA-Leti reported breakthroughs in three projects it considers key to the next generation of CMOS image sensors. The projects involved embedding AI in the CIS and stacking multiple dies to create 3D architectures.

Researchers from MIT’s Computer Science & Artificial Intelligence Laboratory (MIT-CSAIL) used a type of generative AI, known as diffusion models, to train multi-purpose robots, and designed the Grasping Neural Process for more intelligent robotic grasping.

IBM and Pasqal partnered to develop a common approach to quantum-centric supercomputing and to promote application research in chemistry and materials science.

Stanford University and Q-NEXT researchers investigated diamond to find the source of its temperamental nature when it comes to emitting quantum signals.

TU Wien researchers investigated how AI categorizes images.

In Canada:

• Simon Fraser University received funding of over $80 million from various sources to upgrade the supercomputing facility at the Cedar National Host Site.
• The Digital Research Alliance of Canada announced $10.28 million to renew the University of Victoria’s Arbutus cloud infrastructure.
• The Canadian government invested $18.4 million in quantum research at the University of Waterloo.

Events and Further Reading

Find upcoming chip industry events here, including:

Upcoming webinars are here.

Semiconductor Engineering’s latest newsletters:

Automotive, Security and Pervasive Computing
Systems and Design
Low Power-High Performance
Test, Measurement and Analytics
Manufacturing, Packaging and Materials

The post Chip Industry Week In Review appeared first on Semiconductor Engineering.

Atomic layer deposition (ALD) used to be considered too slow to be of practical use in semiconductor manufacturing, but it has emerged as a critical tool for both transistor and interconnect fabrication at the most advanced nodes.

ALD can be speeded up somewhat, but the real shift is the rising value of precise composition and thickness control at the most advanced nodes, which makes the extra time spent on deposition worthwhile.

ALD is a close cousin of chemical vapor deposition, initially introduced in high volume to the semiconductor industry for hafnium oxide (high-k) gate dielectrics. Both CVD and ALD are inherently conformal processes. Deposition occurs on all surfaces exposed to a precursor gas. In ALD, though, the reaction is self-limiting.

The process works like this: First, a precursor gas (A) is introduced into the process chamber, where it adsorbs onto all available substrate sites. No further adsorption occurs once all surface sites are occupied. An inert purge gas, typically nitrogen or argon, flushes out any remaining precursor gas, then a second precursor (B) is introduced. Precursor B reacts with the chemisorbed precursor A to produce the desired film. Once all of the adsorbed molecules are consumed, the reaction stops. After a second purge step, the cycle repeats.

ALD opportunities expand as features shrink
The step-by-step nature of ALD is both its strength and its weakness. Depositing one monolayer at a time gives manufacturers extremely precise thickness control. Using different precursor gases in different ratios can tune the film composition. Unfortunately, the repeated precursor/purge gas cycles take a lot of time. In an interview, CEA-Leti researcher Rémy Gassilloud estimated that in a single wafer process, two minutes per wafer is the maximum cost-effective process time. But two minutes is only enough time to deposit about a 2nm-thick film.

Some process adjustments can improve throughput. Silicon dioxide ALD often uses large furnaces to process many wafers at once. Plasma activation can ionize reagents and accelerate film formation. Still, Gassilloud estimates that 10nm is the maximum practical thickness for ALD films.

As transistors shrink, though, the number of layers in that thickness range is increasing. Transistor structures also are becoming more complex, requiring deposition on vertical surfaces, into deep trenches, and other places not readily accessible by line-of-sight PVD methods. Replacement gates for gate-all-around transistors, for instance, need a process that can fill nanometer-scale cavities.

As noted above, HfO₂ was the first successful application of ALD in semiconductor manufacturing. Its precursors, HfCl₄ and water, are both chemically simple small molecules, whose by-products are volatile and easily removed. Such simple chemistries are the exception, though. ALD of silicon dioxide typically uses aminosilane precursors.⁠[1] Metal nitrides often have complex metal-organic precursor gases. Gassilloud noted that ligands might be added to a precursor molecule to change its vapor pressure or reactivity, or to facilitate adhesion to the substrate. In selective deposition processes, discussed below, ligands might improve selectivity between growth and non-growth surfaces. These larger molecules can be difficult to insinuate into smaller features, and byproducts can be difficult to remove. Complex byproducts can also become a contamination source.

One of the advantages of ALD is its very low process temperature, typically between 200°C and 300°C. It is thermally compatible with both transistor and interconnect processes in CMOS, as well as with deposition on plastic and other novel substrates. Even so, Aditya Kumar and colleagues at GlobalFoundries showed that precise temperature control is important.^⁠[2] TDMAT (tetrakis- dimethylamino titanium) condensation in a TiN deposition process was a significant source of particle defects. To maintain the desired process temperature, both the precursor and purge gas temperatures matter. Introducing cold purge gas into a warm process chamber can cause rapid condensation.

As ALD has become a mainstream process, the industry has found applications for it beyond core device materials, in a variety of sacrificial and spacer layers. For example, double- and quadruple-patterning schemes often use ALD for “pitch-doubling.” By depositing a spacer material on either side of a patterned “mandrel,” then removing the mandrel, the process can cut the original pitch in half without the need for an additional, more costly lithography step.^⁠[3]

Fig. 1: Self-aligned double patterning with ALD spacers. Source: Creative Commons

Depositing a doped oxide on the vertical silicon fins of a finFET device is a less directional and less damaging alternative to ion implantation.[^⁠4]

Selective deposition brings lateral control
These last two examples depend on surface characteristics to mediate deposition. A precursor might adhere more readily to a hard mask than to the underlying material. The vertical face of a silicon fin might offer more (or fewer) adsorption sites than the horizontal face. Selective deposition on more complicated structures may require a pre-deposited growth template, functionalizing substrate regions to encourage or discourage growth. Selective deposition is especially important in interconnect applications. In general, though, a comprehensive review by Rong Chen and colleagues at Huazhong University of Science and Technology explained that selective deposition methods need to replenish the template material as the film grows while needing a mechanism to selectively remove the unwanted material.⁠[5]

For example, tungsten preferentially deposits on silicon relative to SiO₂, but the selectivity diminishes after only a few cycles. Researchers at North Carolina State University successfully re-passivated the oxide by incorporating hydrogen into the tungsten precursor.[⁠6] Similarly, a group at Eindhoven University of Technology found that SiO₂ preferentially deposited on SiO₂ relative to other oxides for only 10 to 15 cycles. A so-called ABC-cycle — adding acetylacetone (“Inhibitor A”) as an inhibitor every 5 to 10 cycles — restored selectivity.⁠[7]

Alternatively, or in addition, atomic layer etching (ALE) might be used to remove unwanted material. ALE operates in the same step-by-step manner as ALD. The first half of a cycle reacts with the existing surface, weakening the bond to the underlying material. Then, a second step — typically ion bombardment — removes the weakened layer. For example, in ALE etching of silicon, chlorine gas reacts with the surface to form various SiCl_x compounds. The chlorination process weakens the inter-silicon bonds between the surface and the bulk, and the chlorinated layer is easily sputtered away. The layer-by-layer nature of ALE depends on preferential removal of the surface material relative to the bulk (SiCl_x vs. Si in this case). The “ALE window” is the combination of energy and temperature at which the surface layer is completely removed without damaging the underlying material.

Somewhat counter-intuitively, Keren Kanarik and colleagues at Lam Research found that higher ion energies actually expanded the ALE window for silicon etching. High ion energies with short exposure times delayed the onset of silicon sputtering relative to conventional RIE.[8]

Adding and subtracting, one atomic layer at a time
For a long time, the semiconductor industry has been looking for alternatives to process schemes that deposit material, pattern it, then etch most of it away. Wouldn’t it be simpler to only deposit the material we will ultimately need? Meanwhile, atomic layer deposition has been filling the spaces under nanosheets and inside cavities. Bulk deposition and etch tools are still with us, and will be for the foreseeable future. In more and more cases, though, those tools provide the frame while ALD and ALE processes fill in the details.

Correction: Corrected attribution of the work on ABC cycles and selective deposition of SiO₂.

References

1. Wenling Li, et al., “Impact of aminosilane and silanol precursor structure on atomic layer deposition process,”Applied Surface Science, Vol 621, 2023,156869, https://doi.org/10.1016/j.apsusc.2023.156869.
2. Kumar, et al., “ALD TiN Surface Defect Reduction for 12nm and Beyond Technologies,” 2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs, NY, USA, 2020, pp. 1-4, doi: 10.1109/ASMC49169.2020.9185271.
3. Shohei Yamauchi, et al., “Extendibility of self-aligned type multiple patterning for further scaling”, Proc. SPIE 8682, Advances in Resist Materials and Processing Technology XXX, 86821D (29 March 2013); https://doi.org/10.1117/12.2011953
4. Kalkofen, et al., “Atomic layer deposition of phosphorus oxide films as solid sources for doping of semiconductor structures,” 2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO), Cork, Ireland, 2018, pp. 1-4, doi: 10.1109/NANO.2018.8626235.
5. Rong Chen et al., “Atomic level deposition to extend Moore’s law and beyond,” 2020 Int. J. Extrem. Manuf. 2 022002 DOI 10.1088/2631-7990/ab83e0
6. B Kalanyan, et al., “Using hydrogen to expand the inherent substrate selectivity window during tungsten atomic layer deposition,” 2016 Chem. Mater. 28 117–26 https://doi.org/10.1021/acs.chemmater.5b03319
7. Alfredo Mameli et al., “Area-Selective Atomic Layer Deposition of SiO2 Using Acetylacetone as a Chemoselective Inhibitor in an ABC-Type Cycle” ACS Nano 2017, 11, 9, 9303–9311. https://doi.org/10.1021/acsnano.7b04701
8. Keren J. Kanarik, et al., “Universal scaling relationship for atomic layer etching,” J. Vac. Sci. Technol. A 39, 010401 (2021); doi: 10.1116/6.0000762

The post Enabling Advanced Devices With Atomic Layer Processes appeared first on Semiconductor Engineering.

Atomic layer deposition (ALD) used to be considered too slow to be of practical use in semiconductor manufacturing, but it has emerged as a critical tool for both transistor and interconnect fabrication at the most advanced nodes.

ALD can be speeded up somewhat, but the real shift is the rising value of precise composition and thickness control at the most advanced nodes, which makes the extra time spent on deposition worthwhile.

ALD is a close cousin of chemical vapor deposition, initially introduced in high volume to the semiconductor industry for hafnium oxide (high-k) gate dielectrics. Both CVD and ALD are inherently conformal processes. Deposition occurs on all surfaces exposed to a precursor gas. In ALD, though, the reaction is self-limiting.

The process works like this: First, a precursor gas (A) is introduced into the process chamber, where it adsorbs onto all available substrate sites. No further adsorption occurs once all surface sites are occupied. An inert purge gas, typically nitrogen or argon, flushes out any remaining precursor gas, then a second precursor (B) is introduced. Precursor B reacts with the chemisorbed precursor A to produce the desired film. Once all of the adsorbed molecules are consumed, the reaction stops. After a second purge step, the cycle repeats.

ALD opportunities expand as features shrink
The step-by-step nature of ALD is both its strength and its weakness. Depositing one monolayer at a time gives manufacturers extremely precise thickness control. Using different precursor gases in different ratios can tune the film composition. Unfortunately, the repeated precursor/purge gas cycles take a lot of time. In an interview, CEA-Leti researcher Rémy Gassilloud estimated that in a single wafer process, two minutes per wafer is the maximum cost-effective process time. But two minutes is only enough time to deposit about a 2nm-thick film.

Some process adjustments can improve throughput. Silicon dioxide ALD often uses large furnaces to process many wafers at once. Plasma activation can ionize reagents and accelerate film formation. Still, Gassilloud estimates that 10nm is the maximum practical thickness for ALD films.

As transistors shrink, though, the number of layers in that thickness range is increasing. Transistor structures also are becoming more complex, requiring deposition on vertical surfaces, into deep trenches, and other places not readily accessible by line-of-sight PVD methods. Replacement gates for gate-all-around transistors, for instance, need a process that can fill nanometer-scale cavities.

As noted above, HfO₂ was the first successful application of ALD in semiconductor manufacturing. Its precursors, HfCl₄ and water, are both chemically simple small molecules, whose by-products are volatile and easily removed. Such simple chemistries are the exception, though. ALD of silicon dioxide typically uses aminosilane precursors.⁠[1] Metal nitrides often have complex metal-organic precursor gases. Gassilloud noted that ligands might be added to a precursor molecule to change its vapor pressure or reactivity, or to facilitate adhesion to the substrate. In selective deposition processes, discussed below, ligands might improve selectivity between growth and non-growth surfaces. These larger molecules can be difficult to insinuate into smaller features, and byproducts can be difficult to remove. Complex byproducts can also become a contamination source.

One of the advantages of ALD is its very low process temperature, typically between 200°C and 300°C. It is thermally compatible with both transistor and interconnect processes in CMOS, as well as with deposition on plastic and other novel substrates. Even so, Aditya Kumar and colleagues at GlobalFoundries showed that precise temperature control is important.^⁠[2] TDMAT (tetrakis- dimethylamino titanium) condensation in a TiN deposition process was a significant source of particle defects. To maintain the desired process temperature, both the precursor and purge gas temperatures matter. Introducing cold purge gas into a warm process chamber can cause rapid condensation.

As ALD has become a mainstream process, the industry has found applications for it beyond core device materials, in a variety of sacrificial and spacer layers. For example, double- and quadruple-patterning schemes often use ALD for “pitch-doubling.” By depositing a spacer material on either side of a patterned “mandrel,” then removing the mandrel, the process can cut the original pitch in half without the need for an additional, more costly lithography step.^⁠[3]

Fig. 1: Self-aligned double patterning with ALD spacers. Source: Creative Commons

Depositing a doped oxide on the vertical silicon fins of a finFET device is a less directional and less damaging alternative to ion implantation.[^⁠4]

Selective deposition brings lateral control
These last two examples depend on surface characteristics to mediate deposition. A precursor might adhere more readily to a hard mask than to the underlying material. The vertical face of a silicon fin might offer more (or fewer) adsorption sites than the horizontal face. Selective deposition on more complicated structures may require a pre-deposited growth template, functionalizing substrate regions to encourage or discourage growth. Selective deposition is especially important in interconnect applications. In general, though, a comprehensive review by Rong Chen and colleagues at Huazhong University of Science and Technology explained that selective deposition methods need to replenish the template material as the film grows while needing a mechanism to selectively remove the unwanted material.⁠[5]

For example, tungsten preferentially deposits on silicon relative to SiO₂, but the selectivity diminishes after only a few cycles. Researchers at North Carolina State University successfully re-passivated the oxide by incorporating hydrogen into the tungsten precursor.[⁠6] Similarly, a group at Argonne National Laboratory found that SiO₂ preferentially deposited on SiO₂ relative to other oxides for only 10 to 15 cycles. Adding acetylacetone (“Precursor C”) as an inhibitor every 5 to 10 cycles — restored selectivity.⁠[7]

Alternatively, or in addition, atomic layer etching (ALE) might be used to remove unwanted material. ALE operates in the same step-by-step manner as ALD. The first half of a cycle reacts with the existing surface, weakening the bond to the underlying material. Then, a second step — typically ion bombardment — removes the weakened layer. For example, in ALE etching of silicon, chlorine gas reacts with the surface to form various SiCl_x compounds. The chlorination process weakens the inter-silicon bonds between the surface and the bulk, and the chlorinated layer is easily sputtered away. The layer-by-layer nature of ALE depends on preferential removal of the surface material relative to the bulk (SiCl_x vs. Si in this case). The “ALE window” is the combination of energy and temperature at which the surface layer is completely removed without damaging the underlying material.

Somewhat counter-intuitively, Keren Kanarik and colleagues at Lam Research found that higher ion energies actually expanded the ALE window for silicon etching. High ion energies with short exposure times delayed the onset of silicon sputtering relative to conventional RIE.[8]

Adding and subtracting, one atomic layer at a time
For a long time, the semiconductor industry has been looking for alternatives to process schemes that deposit material, pattern it, then etch most of it away. Wouldn’t it be simpler to only deposit the material we will ultimately need? Meanwhile, atomic layer deposition has been filling the spaces under nanosheets and inside cavities. Bulk deposition and etch tools are still with us, and will be for the foreseeable future. In more and more cases, though, those tools provide the frame while ALD and ALE processes fill in the details.

References

1. Wenling Li, et al., “Impact of aminosilane and silanol precursor structure on atomic layer deposition process,”Applied Surface Science, Vol 621, 2023,156869, https://doi.org/10.1016/j.apsusc.2023.156869.
2. Kumar, et al., “ALD TiN Surface Defect Reduction for 12nm and Beyond Technologies,” 2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs, NY, USA, 2020, pp. 1-4, doi: 10.1109/ASMC49169.2020.9185271.
3. Shohei Yamauchi, et al., “Extendibility of self-aligned type multiple patterning for further scaling”, Proc. SPIE 8682, Advances in Resist Materials and Processing Technology XXX, 86821D (29 March 2013); https://doi.org/10.1117/12.2011953
4. Kalkofen, et al., “Atomic layer deposition of phosphorus oxide films as solid sources for doping of semiconductor structures,” 2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO), Cork, Ireland, 2018, pp. 1-4, doi: 10.1109/NANO.2018.8626235.
5. Rong Chen et al., “Atomic level deposition to extend Moore’s law and beyond,” 2020 Int. J. Extrem. Manuf. 2 022002 DOI 10.1088/2631-7990/ab83e0
6. B Kalanyan, et al., “Using hydrogen to expand the inherent substrate selectivity window during tungsten atomic layer deposition,” 2016 Chem. Mater. 28 117–26 https://doi.org/10.1021/acs.chemmater.5b03319
7. Yanguas-Gil A, Libera J A and Elam J W, “Modulation of the growth per cycle in atomic layer deposition using reversible surface functionalization,” 2013 Chem. Mater. 25 4849–60 https://doi.org/10.1021/cm4029098
8. Keren J. Kanarik, et al., “Universal scaling relationship for atomic layer etching,” J. Vac. Sci. Technol. A 39, 010401 (2021); doi: 10.1116/6.0000762

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